Interconnect:The new frontier

09/01/1998

A SOLID STATE TECHNOLOGY SERIES

Interconnect: The new frontier

Ed Korczynski, Senior Technical Editor, [email protected]

On-chip interconnect is now one of the most challenging areas of IC processing, though it has not always been so. Until the late 1980s, the greatest challenges to processing lay in forming the active device elements. Interconnects, composed primarily of aluminum and SiO2, were relatively simple and had clear evolution paths for development.

The radical shift in importance came about because chip speeds are now in the hundreds of megahertz range, and each signal sent across the chip barely has time to reach the other side before the next signal is sent. The signal delay is proportional to the product of the dielectric`s capacitance (C) and the conductor`s resistance (R). High-speed logic designers must now contend with the "RC delay."

Changing from aluminum to copper reduces the resistance by ~40%, and changing from SiO2 to a relatively ideal low-k dielectric reduces the capacitance by ~50%. Combined, these two changes should allow chips to operate ~4? faster. However, radically new structures and designs will be needed to enter the gigahertz era, as shown by Keunmyung (Ken) Lee of Hewlett-Packard Laboratories in "On-chip interconnects - Gigahertz and beyond," the first article in Solid State Technology`s Interconnect Series.

In the short term, fabs must decide among the many alternatives represented by copper, various low-k dielectrics, re-routing lines, and additional levels. Each change adds cost, and it`s clear that no one wants to introduce them all at the same time. IC manufacturers will implement these solutions in different orders, as will be explained by X.W. Lin and Dipu Pramanik of VLSI Technology in "Future interconnect technologies and copper metallization," the second article in the series in October.

With so many options and complex tradeoffs, the best combination of processes can be surprising. Roy Iggulden, et al. from the IBM/Siemens DRAM alliance will detail one such solution in "Dual damascene aluminum wiring for Gbit DRAMs," the final part of the series in November.

ED KORCZYNSKI is Senior Technical Editor for Solid State Technology. He received his BS in materials science and engineering from the Massachusetts Institute of Technology. He has more than 10 years of engineering and management experience in process development and equipment marketing. His current interests are thin films, process integration, and plasma and vacuum technology. He is a member of the Materials Research Society. Solid State Technology, 1700 S. Winchester Blvd., Suite 210, Campbell, CA ph 408/370-4833, e-mail [email protected].