Interconnect options grow

09/01/1998

Interconnect options grow

A tremendous amount of worldwide activity is focused around developing on-chip interconnects that can function at ever increasing circuit speeds. While copper conductors and low-k dielectric insulators will be used in the future, it is too risky and expensive to change both at once. Immediate next-generation processes will either change one of them, or neither by extending current processes with more efficient signal routing.

The increasing importance of interconnect processing has generated a dedicated conference, the IITC; the VMIC is another (see box). A summary of some of the more significant presentations at these two conferences follows.

Wireless clock distribution (IITC). Since the speed of planned ICs is expected to eventually reach above 10 GHz, radically different on-chip interconnect schemes will be needed. Optical and superconducting strategies have been proposed, but University of Florida researchers (supported by the SRC and IBM) are exploring the use of microantennae for clock distribution in 10-20 GHz chips. Chips should be ~4 cm wide by 2010, and a central transmitter could eliminate the wires and routing problems for clock signals. Since signals would propagate at the speed of light, there would be no RC delay.

Cu processing at IBM (IITC). IBM showed 0.1 ?m 4.5:1 gaps (produced with e-beam lithography) that were perfectly filled with Cu using ionized PVD (i-PVD) liners and electrochemical deposition (ECD) Cu, indicating that ECD is very extendible. By tightly controlling etch and lithography, IBM eliminates the nitride etch-stop layer that increases overall stack capacitance and RC delay. When the process shifts to include low-k dielectrics, however, the nitride etch-stop will be required. Though the new Cu CMOS 7S chips can run 77% faster than their Al(Cu) predecessors, the calculated greatest factor in the speed increase was wire re-routing, not the change to copper.

IBM`s 6-level copper process consists of CMOS 7S microprocessor; prototype 32-bit RISC CPU; 6.4 million transistors; 0.20-?m process (0.25-?m shrink); 6 levels Cu, 0.63-?m min. pitch; 2? pitch + thickness for M5, M6; and W damascene local interconnect.

SiOF process integration (IITC). Replacing some of the silicon in SiO2 with fluorine lowers the dielectric constant from ~4 to ~3.5, though integration has not been trivial. Lucent and NEC reported on SiOF (also termed "F-SiO2" and "FSG") intra-level dielectric (IaLD) process integration. Researchers compared the newer film to SiO2 IaLD, both with SiO2 interlevel dielectric (IeLD), for a triple-level metal 0.25-?m CMOS process. A measured intrametal capacitance reduction of 12% indicated that the material properties were maintained through the entire process. The IaLD change resulted in a 2% speed improvement for a standard 88-gate ASIC array, but reliability testing was not yet complete.

"Digital" TiN deposition (IITC). For metal barrier layers, it is important to be as thin as possible (to minimize resistivity of the complete conductor structure), while maintaining continuous barrier integrity. Researchers at Samsung grew TiN barriers monolayer by monolayer with NH3 and TiCl4 (commonly called "tickle"), without requiring the high temperatures of standard CVD TiN processes using these precursors. The new process avoids carbon contamination seen with metal-organic CVD (MOCVD) precursors, and the Cl content is <1% for a 500?C process. Pulse times and pressures are in the range of single digit second and Torrs. With 2 ?/cycle deposited (roughly one monolayer), the final film`s contact resistance was ~200 ?m?-cm. However, p+ contact resistance and n+ leakage current results need improvement, and increasing the deposition speed to 20?/cycle raised the final contact resistance to ~600 ?m?-cm.

CVD Cu seed/fill layers (VMIC). CVC showed that MOCVD Cu can fill 7:1 aspect-ratio (AR) 0.15-?m trench/via dual-damascene structures, but the deposition rate is fairly low. The maximum allowable MOCVD rate for void-free filling of ~0.15-?m features is about one-fourth of the allowable rate for ~0.50 -?m features. CVC also calculated the requirements for Cu ECD seed layers. To maintain ECD uniformity, the Cu film should have maximum resistivity of 0.6 ?2 to achieve an electroplating uniformity of <5% on a 200-mm wafer, translating into a minimum Cu seed layer thickness of ~500 ?.

Ion plating Cu seed layers (VMIC). A new ion plating process from Sumitomo Heavy Industries (named "URT" after the developing researchers` initials) could be an alternative to ionized-PVD for the deposition of Cu seed layers. The technique uses a gradient pressure type Ar plasma gun 100-200 A current to produce a 1011-1012 density plasma jet. Directed by permanent and coil magnets, the plasma impinges upon a Cu target to vaporize Cu. The vaporized Cu is ionized as it travels through the impinging beam to finally strike the silicon wafer. The researchers filled 0.4 ?m 2:1 AR tapered vias in 3 min. with this new process, representing ~20 ?/sec. deposition rate.

Spin-on glass stabilization (VMIC). For partial etch-back (PEB) spin-on glass (SOG) applications, Mosel Vitelic researchers presented results showing SOG stabilization using boron implantation. High-energy ion bombardment condenses the SOG, producing a more stable film. Using B requires a higher dosage and degrades the film`s planarity, while BF2 requires less dosage to achieve film stability and there is no planarity loss. The treated films absorbed less moisture, and there was a direct correlation between dose and reduction in moisture uptake. 5?1014 BF2 was the minimum dosage required to eliminate moisture absorption. - E.K.