On-chip interconnects- gigahertz and beyond
09/01/1998
FIRST IN A SERIES
On-chip interconnects - gigahertz and beyond*
Keunmyung (Ken) Lee, Hewlett-Packard Laboratories, Palo Alto, California
Conventional VLSI on-chip interconnect systems will soon hit multi-GHz performance barriers. Metal planes/meshes and larger cross-sectional area signal lines can provide an impedance-controlled environment to solve the long lossy line problem. Planes also help distribute power with minimal AC/DC noise. As an additional feature, integration of passive elements into on-chip interconnects will be very useful in realizing fully integrated "system-on-chip" integrated circuits.
The performance of integrated circuits (ICs) has been increasing exponentially, based on the scaling of devices and interconnects along with new chip architectures and design methods. As we scale down the feature size of on-chip interconnects, increase the size of chips, and boost operating-speeds at the same time, we begin to hit serious electrical problems. These include excessive signal delay due to long lossy lines, signal skew, signal noise, and power supply distribution.
Many of these problems are not actually new to electronic system design from the broadest perspective. A similar set of problems has been dealt with in multichip modules (MCMs), printed circuit boards (PCBs), and entire systems comprising many PCBs. Now that a single chip is an entire system (the concept of system-on-chip), the structure of on-chip interconnects should become more like those of MCMs and PCBs: with many more signal layers and planes.
On-chip interconnects were somewhat immune from electrical problems when their lengths were much smaller than the wavelengths of signals within the chip. However, as the operating frequency of chips increases beyond 1 GHz, long interconnects on large chips behave like distributed electrical lines. In other words, they behave more like signal traces on high speed PCBs. The signal propagation in on-chip lines is actually worse because of the high loss of the lines. This also makes distribution of power supply current to the entire chip very challenging for high-power chips.
Here we address the electrical problems in on-chip interconnects in terms of signal propagation and power supply distribution for future multi-GHz chips. Also, desired features of the future interconnects for system-on-chip are discussed along with design tool issues.
Signal delay, skew, and noise
On-chip signal lines can be electrically categorized into two groups: short local interconnects and global interconnects. For the first group, the main issue is density. These short connections are usually done with the first and second level metal layers and scaling down of these layers will continue for multi-GHz chips because there are no fundamental electrical limits with these layers.
The situation is very different for global interconnects, however. Global routing lines as long as one side of a chip are not uncommon in current VLSIs, and the trend will continue as chips in corporate more functional units [1]. Current multilevel interconnect systems provide coarse upper metal layers for global routing, but the design rules that are used in current chips are not suitable for multi-GHz signalling because the lines are too resistive. It takes several reflections for a signal to rise after the initial time-of-flight delay (Fig. 1).
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Figure 1. Delays in a 2-cm-long on-chip signal line, with an input 100 psec pulse. Lossy RC delays account for most of the delay.
In order to avoid excessive loss in global routing, repeaters (similar to the amplifiers in telecommunication lines) are commonly used in long signal lines of current chips. However, repeaters themselves have internal delays, and it is not always straightforward to insert repeaters in signal lines because of physical constraints. Even with repeaters, the signal delay through a 20-mm line is about 1 nsec, which means that the data cannot be latched within the cycle time of a 1-GHz chip. Another way to eliminate the excessive delay is to use large cross-sectional area signal lines (Fig. 2), though space constraints limit this approach in high-density ICs.
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Figure 2. Delays in a 2-cm-long MCM signal line, with an input 100-psec pulse. The larger cross-sectional area of the line effectively eliminates the RC component of the delay, leaving only the lossless time-of-flight component.
Another problem with current global routing layers is that there is no control over the effect of neighboring layer interaction, which introduces timing skew between data bits in the same bus. Timing skew becomes worse as the width of the bus increases.
All these problems can be solved if low-loss controlled impedance transmission lines are available for global on-chip interconnects. The same evolution has already occurred in PCB designs. As system speed became faster, single- and double-layer boards were replaced by impedance-controlled multilayer boards.
It will be ideal if thin-film Cu/low-k MCM type interconnects can be implemented as global routing layers for on-chip signals (Fig. 3). The typical 10-?m-wide ? 3-?m-thick copper line surrounded by copper planes/meshes in a MCM can carry signals for up to 6 cm, and the delay for a 20-mm line is only about 135 psec. This type of interconnect provides sufficient frequency headroom for chips to move into multi-GHz speeds. But when we face the hard limit of the speed of light within the dielectric - several process generations from now - asynchronous communication between functional blocks within a chip will be unavoidable, just as it is in modern telecommunications.
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Figure 3. Conceptual schematic of a multi-GHz on-chip interconnect system displaying similarities to MCM/PCB interconnect structures.
Impedance-controlled low-loss lines not only reduce signal delays but also cut skew and crosstalk. Because signal lines are referenced to the surrounding planes, the propagation delay is not influenced by the signals in the other layers. This results in tight skew control of the signal lines within a bus. Also, electromagnetic coupling can be limited by proper spacing between the lines. Excessive inductive coupling, which occurs when many signal lines share a single ground trace without planes nearby, can thus be avoided.
It has been proposed that the impedance-controlled low-loss inter-chip lines of a chip carrier could provide intra-chip signal connection [1]. However, history shows that integrated monolithic on-chip interconnects are always more economical than MCM or PCB interconnect solutions. This economically driven trend will continue if on-chip interconnect technology adds one more hierarchy of interconnects (with the characteristics described above).
In terms of materials, higher conductivity for metal and lower dielectric constant for dielectric are always better choices. However, the high-frequency dissipation factor of dielectric materials has to be carefully examined because the dielectric loss can be a significant portion of the loss of high-frequency signals.
Power supply distribution
Most high-powered chips have a couple of metal layers dedicated to global power supply. When an area-array type of chip connection, such as a solder-bump, is available, a single plane power/ground mesh can work fairly well without excessive DC drop through the network. When power/ground connections are made only at the edge of a chip, however, two entire planes may have to be dedicated to power supply in order to maintain a low resistance voltage drop [2].
The inductive voltage drop due to current surges can be quite substantial in both cases, because the on-chip power supply inductance can be a few nH and the edge rate of the power supply current is in the order of nanoseconds. The sources of the current surges are the drivers for the output pads and internal logic switching, especially at clock edges. Most of the literature concentrates on the transient power noise - from current surges through inductive paths (dI/dt noise) - that arises from output drivers, but internal logic is usually the greater source of this noise in actual high-performance processors.
The bypassing at this level is mostly done with hidden on-chip capacitance between VDD and GND, which includes the reverse biased diodes in wells and source/drain regions, the gate capacitance, and intermetal capacitance. Together, these capacitances provide local charge reservoirs for switching - as large as a few hundred nanofarads for large processor chips. These capacitances filter out the high-frequency components of power supply noise before it goes out from the chip. Since it is the most effective way of reducing the noise, extra on-chip bypass capacitors are sometimes intentionally built in a chip using the gate oxide as a dielectric, which may reduce chip yield due to the increased gate area.
For future multi-GHz chips, larger amount of on-chip bypass capacitance will be required because of the increased power, lower supply voltage, and larger switching current [3]. If on-chip interconnect processing can produce high-density bypass capacitors, as shown in Fig. 1, it will greatly improve chip noise performance. Packaging cost would also be reduced because less bypassing would be required at the packaging level, though clever materials engineering is needed to integrate high-k dielectric thin films and metal planes.
Passive components
Besides impedance-controlled low loss lines and power planes with high-k dielectrics to solve the two major problems of multi-GHz interconnects, there are some components that will be extremely useful in future multilevel interconnects as we move toward the era of system-on-chip, which will involve the integration of digital and analog functions. In many analog functions, well-controlled passive elements, including resistors, capacitors, and inductors, are required.
Resistors generate current references and terminate signal lines. Just like the buried resistor in printed circuit technology, resistor-on-chip will help reduce overall system cost. Capacitors and inductors are used in many analog functions, such as resonators and charge pumps. In order to obtain large values of capacitance and inductance within a limited area, techniques for selective deposition of high dielectric and magnetic materials should be developed.
Conclusion
On-chip interconnects have always been the most cost-effective way to make electrical connections between the functional blocks of a system. As the operating speed of VLSI chips increases beyond 1 GHz, however, major adjustments of the on-chip metal design are required, because of the electrical limits of the current metal structures. Adding multiple plane structures with larger signal lines will solve the electrical problems in signal delay and power supply. In addition, selective deposition of high-k dielectric and magnetic materials will help realize fully integrated system-on-chip ICs.
References
1. E.E. Davidson, B.D. McCredie, W.V. Vilkelis, "Long Lossy Lines (L3) and Their Impact Upon Chip Performance," IEEE Trans. Comp. Packaging, Manuf. Technol., Part B, Vol. 20, No. 4, pp.361-375, Nov. 1997.
2. B.A. Gieseke, et al., "A 600 MHz Superscalar RISC Microprocessor with Out-of-Order Execution," ISSCC97, pp. 176-178, Feb. 1997.
3. K. Lee, A. Barber, "Modeling and Analysis of Multichip Module Power Supply Planes," IEEE Trans. Comp. Packaging, Manuf. Technol., Part B, Vol. 18,No. 4, pp. 628-639, Nov. 1995.
*Based on a work originally presented at the 1998 International Interconnect Technology Conference, sponsored by the IEEE Electron Devices Society.
KEUNMYUNG (KEN) LEE received his BS in electronics engineering from Seoul National University, Seoul, Korea, in 1980, and his MS and PhD degrees from the University of California, Berkeley, in 1982 and 1985, respectively, both in electrical engineering and computer sciences. Since 1985 he has been with Hewlett-Packard Laboratories, where he developed interconnect simulation programs, which later became the Raphael program of Technology Modeling Associates, Sunnyvale, CA. He is currently a principal project engineer. Hewlett-Packard Laboratories, P.O. Box 10490, Palo Alto, CA 94304-0969; ph 650/857-5348, fax 650/236-9675, e-mail [email protected].