MRS Meeting Report
07/01/1998
Cu, low-k dielectrics top MRS meeting agenda
Ed Korczynski, Senior Technical Editor
With some sessions spilling out into hallways, the 1998 Spring Materials Research Society (MRS) meeting in San Francisco updated some 2000 attendees on the latest work on copper, low-k as well as high-k dielectrics, and a wide variety of other topics in the forefront of semiconductor and thin film processing and materials.
IC processing has developed to the point that easy and obvious gains in materials properties are already accomplished, and further gains will involve subtleties and interdependent second-order effects. These complex relations between microstructures, processing technologies, and macroproperties are at the heart of materials research.
Cu barrier layers
In a paper entitled, "The effect of liner materials and dimension on the microstructure of damascene-fabricated Cu interconnects," TI researchers showed that subtleties in the process integration of barrier layers can alter the final properties of copper interconnects. In general, it appears that results from the stacked depositions of blanket films do not necessarily translate into results in complex 3D structures.
They observed both <111> and <200> crystallographic orientation in electrochemically deposited (ECD) copper films, and determined that TiN barrier layers may be superior to Ta. Despite multiple competing phenomena, there are only two primary distinctions between ECD reaction regimes: template-controlled growth and geometry controlled growth.
Template control refers to the crystallographic orientation of the ECD seed/barrier layers that can function as a "template" for the growth of copper with similar atomic orientation. For example, Al grows in a <111> orientation on either TiN <111> or Ti <0002>.
For a conformal Ta liner in a trench, both the bottom and the sidewalls are formed with <0002> orientation. When a copper ECD film grows above such a liner, the copper grains follow the template and begin growing out from all surfaces. When the grains meet in the middle to completely fill the trench, the result is a final copper line with mixed orientation (Fig. 1a-c).
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Figure 1. Simplified representation of the difference between templated (a-c) and geometric (d-f) ECD Cu growth in a damascene structure. The preferred orientation of some barrier materials a) induces oriented Cu to grow from the sidewalls b), resulting in a final structure with mixed grains c). Barrier materials without preferred orientation d) don`t template Cu growth on sidewalls e), so the that the geometry of the trench induces single-crystal growth from the bottom up f).
In contrast, TiN liners do not provide an energetically favorable template for copper growth. Without the template mechanism to control growth, the sidewalls don`t influence the deposition and copper grows under geometric control (Fig. 1d-f). A common example of geometric control is the recrystallization of Al-filled trenches.
Micron-scale metal lines can be formed such that each crystalline grain fills the whole width of the line. The resulting line looks like segments of a bamboo stalk, with transverse grain-boundaries separating rows of single grains.
As further proof of the geometric effect, TI researchers saw a strong linewidth dependence on final copper grain orientation. As linewidths are reduced, the percentage of copper in the <111> orientation increases. Thermal annealing further improves the percent <111> orientation, forming near-bamboo structures for linewidths between 0.7 and 0.4 ?m.
It is clear that the final orientation of ECD Cu lines depends on the liner material and the width of the line. However, liner materials do not have a major influence on grain size. The researchers have not yet determined the effects of orientation on reliability.
However, due to the template effect, liners that result in good Cu orientation in blanket films might not result in good orientation in damascene lines and vias.
Cu reliability
C.-K. Hu, of IBM`s T.J. Watson Research Center, presented Cu reliability results to a standing-room-only crowd in a joint session between symposia covering low-k dielectrics and microelectronics reliability. IBM results confirm that Cu lines are never perfect "bamboo" structures, but are generally bamboo-like single-crystal across a given line.
In general, it is known that metal interconnect failures are caused by the diffusion of metal atoms in an electric field. The researchers conducted an atomic drift experiment in which atoms are driven by the electron flux in an electric field.
For side-by-side comparison, damascene process flows produced test chips with both Cu and Al metallizations, and both incorporated low-k polyimide dielectric layers. The test conditions were 5-35 ?A/cm2 in a 10-30 torr vacuum, using a complete 2-level interconnect structure.
CVD-fill Cu lines exhibited near-bamboo structure in sub-0.5-?m lines, moving to more mixed structures as linewidths increased, until becoming fully multicrystalline at 2 ?m. However, the electromigration results were very close, which means that grain-boundaries cannot be the diffusion path for electromigration atomic flux. In a case where grain-boundaries are possible diffusion paths, a fully multicrystalline line allows a million times more diffusion than a pure single-crystal line.
The similarity between single- and multicrystalline line electromigration results supports the conclusion that the diffusion path is along the Cu barrier layer. If true, this suggests that the quality of the interface between the barrier and the copper seed layer (or the copper fill in a CVD-fill process) is the single most important variable in the lifetime of Cu lines.
The researchers also investigated the influence of the surrounding dielectric material on lifetime. Because of the barrier layer, Cu is constrained and never contacts the dielectric. Consequently, the dielectric is irrelevant and doesn`t influence Cu electromigration.
Passivating low-k HSQ
Hydrogen silsequioxane (HSQ) (k~3) has been in volume production at TI (for DSPs) for several years now as a nonetchback spin-on dielectric (SOD). HSQ, and other low-k SOD, absorb moisture and solvents during extended exposure. HSQ sidewall exposure post-etch (before metal deposition) is the most difficult to protect.
TI researchers developed a NH3/N2 plasma treatment to densify and create a thin Si-O-N passivation layer on sidewalls. Nitrogen content as high as 13.7 atomic% was found in the outer layer, decreasing to ~3% at 40-60 ? film depth. Since the nitrogen remains in a top surface layer, the bulk k value should not be significantly reduced by this process.
Stress hysteresis, XPS, and TOFSIMS results showed the plasma-treated HSQ had better thermal and mechanical properties. Hydrogen evolution results clearly show the improved thermal stability (Fig. 2); the passivated film was clearly superior to both the baseline and the 200-nm oxide capped structure.
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Figure 2. Hydrogen silsequioxane (HSQ) low-k dielectric layers have limited thermal stability, typified by hydrogen out-gassing from broken bonds. Plasma nitridization creates a thin capping layer that keeps hydrogen in the film better than oxide and far better than an uncapped film. The knee in the uncapped curve at 370?C represents serious film breakdown.
Porous low-k dielectrics
An evening roundtable session covered the development of manufacturable processes for the deposition of interlevel dielectrics (ILD) with k<2. It`s commonly known that using lower dielectric constant materials reduces interconnect delays that can slow down chip speed. With SiO2 k~4, air =1, and polymers ~2-3, the lowest k materials are fabricated like foams with two phases. One stronger phase holds the overall form, while a second phase (such as a gas or a light polymer) fills the pores.
The second phase is always a slightly lower k material, so increasing the percent of the volume that is taken up by pores (vol%) lowers the overall k of the layer. However, the pore vol% cannot rise too high or not enough of the first phase remains for mechanical integrity.
Also, continuous strings of open pores compromise device performance and manufacturability, so SOD low-k films will probably need to be formed of discrete closed pores of limited vol%. The "Band-Aid" approach of a relatively dense liner (such as oxide) may work, but it requires a more difficult process flow and increases the overall dielectric constant. Pores inherently reduce the thermal conductivity, which leads to increased Joule heating induced electromigration. Overall, the problem is not the basic material engineering; the difficulty is in integrating porous materials into a high-yielding production process.
The best plan is to start with a low-k bulk organic material and use only ~20 vol% voids; 20% voids in 2.6 k material yields 2.0 k. After such a material is proven in pilot lines, then the pore volume could be slowly increased as process experience is gained.
Also, pores must be small relative to interconnect feature sizes, and there must be no "killer pores" of large size. Since Cu barrier layers will be ~10-nm thick, the pore size must be smaller or the barrier may not completely cover any exposed pores in etched vias. For 0.1-?m structures, 5-nm pores of very tight distribution will be needed - and that means near molecular control. Nanopore founder,
Doug Smith, stated, "Closed pores are a great idea, but at 5 nm the distances between pores is so small and the internal pore surface area is so large that there will probably be high water absorption."
An unexpected addition to the roundtable discussion was a proof-of-concept presentation on an entirely new deposition technique to produce "meso-structured" films. C. Jeffrey Brinker, University of New Mexico professor and Sandia National Laboratory scientist, surprised the attendees by declaring that this new process meets or exceed all specs without a single drawback.
The Sandia process creates highly ordered pores on the order of 5-100 nm with remarkably tight size distributions (Fig. 3). Sandia templates the films with surfactant molecules, so the process relies on differences in surface energies across molecular distances. Films grow in a sol-gel dipping process, reportedly reaching full thickness in several seconds. Typical films thicknesses are 0.5-2.0 ?m, and a dielectric film of 1.5 k was formed (though these results are very preliminary).
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Figure 3. Cross-section of a new "meso-structured" porous low-k dielectric, showing molecular control over the pore size distribution. (Source: Sandia National Lab.)
The work has been extended by preparing organosiloxane frameworks (to impart hydrophobicity) with a wide range of molecular templates to arrive at different pore vol% and final k. Sandia entered into a CRADA agreement with Air Products/Schumacher to further develop this process.
Integrating Cu and a-CF
NEC researchers, Matsubara, Endo, et al., looked into the integration of Cu with amorphous carbon-fluoride (a-CF, a-CF, or "FLAC" for fluorinated amorphous carbon) - the leading low-k CVD process. With ~50% fluorine, the material had a k of 2.5 and good adhesion to SiO2. The deposition rate was 150 nm/min. Test structures were single damascene without vias for integration simplicity (see table).
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A TiN antireflective coating (ARC) is normally needed for lithography. For an a-CF layer on Cu, however, DUV (248- nm) light reflection is only 10% (compared to 40% for a 2-?m oxide top layer) after annealing at 400?C in N2 for 30 min. An ARC will be less important for this combination of interconnect materials.
Cu must remain in lines/vias and it must not oxidize. The researchers evaluated Cu oxidation thickness vs. temperature for post-formation anneal in air. A 100-nm thick copper oxide formed at 200?C, thus oxygen easily diffuses through a-CF at 200?C. However, Cu doesn`t diffuse into a-CF at <400?C.
Cu line resistivity was 2.3-2.4 ?W-cm at 0.5 ?m linewidth in the complete structure, though other preliminary electrical results were mixed. As deposited leakage current was ~10? that of SiO2 but 350?C annealing didn`t make it any worse. Also, the ~2 MV breakdown voltage was roughly 10? better than SiO2.
W CMP reaction mechanisms
Though CMP is still best described as an art instead of a science, two full days of presentations highlighted the state of the world`s understanding of the fundamental reaction mechanisms in both dielectric and metal CMP. In one of the better presentations, University of New Mexico researchers (along with researchers from Sandia, where most of the work was done) explained why the classic Preston equation (that describes oxide CMP) doesn`t really fit W CMP.
The New Mexico group used a slurry composed of colloidal alumina and KIO3, buffered to pH 4 using potassium hydrogen phthalate (PHP). Alumina concentration, pressure, and temperature all increase the W removal rate, but there is not a direct correlation between process temperature and removal rate. A summary of the reaction kinetics indicates that process temperature is independent of KIO3, but there is an interaction between the colloid and the W surface.
David Stein, U. of NM presenter, said, "All manufacturers stated that their colloids were pure alumina, but our analysis showed that they certainly are not. Alumina is not alumina. The chemistry of the colloid plays a large part in the polishing process." Different phases of Al2O3, Gibbsite (Al(OH)3), and Bohmite (AlO(OH)) were detected in the various alumina colloids.
There have been four basic mechanisms proposed to explain tungsten CMP - passivation and abrasion, direct mechanical abrasion by the colloid, trans-granular fracture assisted by inter-granular chemical attack, and atomic scale adhesive wear. However, the first two of these mechanisms are now proven to be wrong.
Electrochemical oxidation rate measurements and results from in-situ potentiostatic control of the metal indicate that passivation and abrasion (corrosive wear) is not the predominant mechanism. Direct mechanical abrasion of W by the colloid cannot be the mechanism, because the depth and number of plow marks is not proportional to polish rate. Both empirical results and theoretical models disprove simple mechanical abrasion.
The researchers focused on the interactions between colloids and the surface, anticipating that the friction force would vary with pH. The researchers mounted individual alumina particles to AFM tips, and then dragged each particle over a W surface in different solutions while detecting friction force. Using the same alumina particles on AFM tips, they obtained the adhesion force. Results indicate that atomic-scale adhesive wear mechanisms dominate W CMP.
High-k gate dielectrics
In a roundtable discussion on ultra-thin gate dielectrics, representatives from both Intel and TI agreed that a new, high-dielectric constant gate material - with an equivalent oxide thickness <1 nm - will be needed in production by 2006. To allow for all of the needed process R&D, integration, and reliability work, the material and the basic process need to be developed in the next two years. It is likely that any new high-k material will have to prove itself in DRAMs before anyone uses it as a gate dielectric in production.
The difficulty with using any of these more complex oxides is that their more complex structures tend to be inherently less stable than simple SiO2. For example, tantalum pentoxide (Ta2O5) can react with SiO2 at elevated processing temperatures. Barium strontium titanate (BST) has a higher dielectric constant, higher complexity, and less stability.
There are still six to eight years remaining of the current oxynitride production process, with the possibility of a nitride process before the move to exotic high-k materials. However, if high-ks are needed when predicted by the NTRS, then nitride gate processes may only be viable for one device-generation. If so, fabs may choose to skip directly to the high-k material and to avoid the cost of integrating nitride gates.
It`s certain that RTP systems will be needed for gate formation, if only for R&D. Production volumes may require batch processing. However, the gain of an additional process degree of freedom from separating the deposition from the anneal makes RTP an attractive option. The key to any approach is interface control, and RTP could be used to modify the interface even if a furnace does the actual deposition.
Topics at MRS
The 1998 spring meeting of the Materials Research Society (MRS) gathered together some 2000 attendees who work in microelectronic, biomaterials, and other high-tech materials fields for a full week of parallel symposia in San Francisco, April 13-17. With multiple sessions in parallel, attendees moved from one presentation room to another throughout each day, and the most interesting sessions could be easily seen by the crowds overflowing into the halls.
Semiconductor related symposia included the following topics:
Defect & Impurity Engineered Semiconductors and Devices
Low-Dielectric Constant Materials & Applications in Microelectronics
Wide-Bandgap Semiconductors for High Power, Frequency, and Temperature
Hydrogen in Semiconductor Materials
Advances Interconnects & Contact Materials & Processes for Future ICs
Electronic Packaging Materials Science
Materials Reliability in Microelectronics
Microelectromechanical Structures for Materials Research
Materials Issues in CMP
Electron Microscopy of Semiconducting Materials & ULSI Devices
Rapid Thermal and Integrated Processing
Silicon Front-end Technology - Materials Processing & Modeling
Epitaxy and Applications of Si-based Heterostructures
There were also multiple symposia covering developments in flat panel display and information storage technologies.