Chip scale and flip chip: Attractive solutions
07/01/1998
Chip scale and flip chip: Attractive solutions
Pieter Burggraaf, Senior Technical Editor
Just as surface-mount packaging technology (SMT) gradually won over converts from through-hole technology, chip- scale packaging (CSP) is now gaining as a replacement for SMT. Unlike the previous transition, however, rapidly accelerating microelectronic systems` demands, particularly related to system size and chip integration gains, seem destined to drive the adoption of CSP quite rapidly - some forecasts show up to 100% compound annual growth rate. CSP itself is in an application`s race with its ultimate class - flip-chip direct chip attach (FC-DCA). In the past six months, remarkable new FC-DCA technology has emerged as a cost-effective packaging alternative that overcomes classic flip chip drawbacks.
Still lost in a sea of more established packaging types, chip scale packaging (CSP) and its ultimate form - flip-chip direct chip attach (FC-DCA) - are seemingly the inevitable solutions for microelectronics-system size, weight, and performance limitations generally attributable to surface-mount technology (SMT). Conquering these limitations is so critical to industry progress, to competition among systems suppliers, and even for enabling the leading edge of semiconductor technology itself, that rapid progress is being made in making chip scale more production-ready, despite the small forecast markets for CSP and FC-DCA through 2001. Although there is a list of potential CSP and FC disadvantages, we are seeing an increasing number of innovative new technologies chipping away at them.
A simple example of just the system-footprint power of CSP is seen in Xilinx`s new 7 ? 7-mm package for complex programmable logic (the XC9536); input-output (I/O) is via an array of 48 0.8-mm solder balls (Fig. 1). This "die-level-assembly" package is approximately one third the size of the 44VQ very thin quad package, one of several quad flat packs (QFPs) it replaces. ("Die level" refers to conventional singulated-die assembly in semiconductor manufacturing`s back end.) The XC9536 is the first programmable logic IC in a CSP, making it ideally suited for a growing number of size-sensitive applications, including PCMCIA cards, PC add-in cards, and portable and wireless systems.
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Figure 1. This new CSP from Xilinx attaches an IC, still using wire bonding, to a plastic substrate that provides bonding pads and routing to 48 solder balls.
Defining the markets
According to Dataquest, the opportunities for CSP in 1998 will be just a 325-million-unit blip (~0.5%) in the 62-billion-unit worldwide IC package market forecast for this year (Fig. 2). The big market segments are still small outline (SO) and QFP SMT packages, which combined in 1998 should amount to 50 billion units (~80%). Similarly, Dataquest forecasts the 1998 opportunities for flip chip at 380 million units (Fig. 3).
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Figure 2. Forecast of CSP opportunities by product compared to the worldwide IC package forecast, both shown in millions of units. The numbers in parentheses refer to the range in numbers of units between 1997 and 2001. (Source: Dataquest)
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Figure 3. Forecast of flip chip opportunities by product compared tothe worldwide IC package forecast, both shown in millions of units. Thenumbers in parentheses refer to the range in number of units between 1997 and 2001. (Source: Dataquest)
The real market message, however, is growth. The various market research organizations that watch packaging trends tag compound annual growth rates (CAGR) for CSP and FC anywhere from 50% to exceeding 100%. Indeed, CSP is universally tagged as the fastest growing segment of the package market.
The Tessera influence
The interest and potential today in CSP owes a great deal to the kick-start provided over the past few years by Tessera`s (San Jose, CA) flexible interposer ?BGA package. ("Interposer" is the electrical interconnection structure between an IC and its package.) Aside from size, this package`s flexibility decouples IC thermal expansion from the package substrate, an important aspect of its reliability performance. Intel`s qualification and selection of the ?BGA for its flash memory was certainly a CSP benchmark. Today, application of the Tessera package is increasingly favored by many others licensees, including Amkor Electronics, Flexera, Hitachi Semiconductor, Hyundai Electronics, Mitsui High-Tec, ReadRite, 3M, Texas Instruments, and others. Tessera supports the CSP concept with its San Jose based "Zinger" manufacturing line that will be able, at full capacity, to process one million ICs/month in ?BGA packages.
Within a relatively short time, the ?BGA and other early CSP solutions seemed to establish the 1.2?-size and 0.8-mm-ball as de facto rules for CSPs - the achievable package is usually =1.2? the die size and for array CSPs solder ball pitch is =0.8 mm. Since the introduction of the ?BGA, the selection of 1.2? technologies includes - among others - Motorola`s rigid interposer SLICC (slightly larger than IC chip) and Amkor`s rigid interposer ChipScale BGA. One of the newest CSP technologies is that from ShellCase (Jerusalem, Israel).
ShellCase
ShellCase has developed a "wafer-level" packaging process to produce its ShellPack peripheral-leaded CSP with 0.3-mm lead pitch and Shell-BGA area array CSP with 0.5-mm ball pitch (Fig. 4). These CSPs range from 0.3 to 0.5-mm thick and are typically no more than 100 ?m larger than the IC`s length and width. The process is capable of producing array CSPs with up to 320 contacts from a 12.5 ? 12.5-mm die.
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Figure 4. A Shell-BGA CSP and its cross-section showing the thin silicon substrate sandwiched between protective layers on top, bottom, and sides.
Briefly, the ShellCase process bonds a thin glass layer to the active surface of a completed silicon wafer. The wafer is background, and etching individualizes dies but leaves them in wafer form. The grooves and dies are covered with an inert epoxy. Then, deep notches drawn between each die expose I/O-pad cross-sections that are contacted with deposited gold. This metal layer is patterned with a lithography step to bring leads to the upper surface, where solder bumps are deposited. Finally, wafer dicing separates the now individually packaged die. The ShellCase process is not limited by any prerequisite of wafer re-layout; the only requirement is free =100-?m wide scribe grids.
The ShellCase concept provides the mechanical and environmental protection associated with conventional packaging. These packages can be board assembled with common SMT techniques, tools, and materials. Like most CSP approaches, the short leads give Shell-BGAs low parasitic inductance and capacitance, reducing high-frequency delays and improving speed while attenuating ground bounce. The package thinness gives efficient heat dissipation (i.e., 5 W with internal temperature rise below 75?C).
Interestingly, ShellCase engineers claim the Shell-BGA is one of the most difficult packages to open, compared to plastic packages or DCA, enabling better passive design security at the systems level. Tampering or forcing open the package causes the die to self-destruct.
User-programmable chipset-manufacturer Xicor (Milpitas, CA), a semiconductor manufacturer involved in the development and commercialization of this technology, is an early licensee of ShellCase`s wafer-level CSP manufacturing process technology and fabrication services. ShellCase is also part of Europe`s Circuits Ultimate Miniaturization Utilizing Multi-Layer Build Up Substrates (CUMULUS) initiative, where its packaging expertise is being used with passive devices and with memory and logic ICs.
Wafer level CSP fabrication
The "wafer level" CSP process used by ShellCase and others (discussed below) is a very significant part of CSP evolution. It is batch assembly that begins with completed whole wafers and uses conventional wafer processing equipment and processes. As the ShellCase process shows, packages are formed while ICs are still in wafer form. In essence, one process sequence simultaneously fabricates packages for the hundreds or more ICs on a given wafer. Then the wafer is diced into individual packaged ICs. The significance of eliminating conventional singulated-die-level assembly processing is a key goal in developing new CSP schemes.
ChipScale
ChipScale`s (San Jose, CA) "peripherally leaded" Micro SMT process is a popular wafer-level process in use by Analog Devices, IBM, National Semiconductor and several manufacturers of passive components, including recent start-up Intarsia, which was formed by Dow Chemical and Flextronics Intl. ("Peripherally leaded" refers to rows of I/Os along a package side, where for CSPs the length of the package is ~1.1? the length of the chip.) Micro SMT is a wafer-level technology where "beam lead"-like I/Os are built into scribe lines between individual die.
The adoption by Intarsia and others of this technology to package thin-film passive components, indicates confidence that the process will provide reduced costs, along with smaller package size and increased performance. Passive or discrete components and all peripherally leaded devices are recognized as major volume opportunities for CSP application (see Fig. 2). The passive device market, particularly, is extremely cost sensitive. Some industry estimates show that up to 50% of system board space is dedicated to passive components. Thus, replacingconventional SMT packaging with CSPs will yield a tremendous saving in board space.
Like many new CSP suppliers, ChipScale has addressed both peripheral and array technology. Its new Micro Grid Array process uses the Micro SMT peripheral structure`s patented post-and-beam technology (Fig. 5). However, the leads are fabricated beneath the chip and do not require the extra silicon area that Micro SMT technology uses in scribe lines. The new structure can be used for both peripheral and array packages and is targeted at those devices that do not require simultaneous top and bottom interconnect, as is required for discrete devices. Although this CSP grid array format has the potential to handle higher lead counts, ChipScale is targeting <68-lead applications.
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Figure 5. ChipScale`s wafer-level process includes deposition of epoxy posts and a dielectric layer. Gold beams are routed to open bond pads and plated with solderable metal.
FC versus CSP
Flip chip (FC) technology (i.e., upside down placement of bare-bumped dies) is often used as a replacement to wire bonding as part of a CSP solution. Similarly, FC is also widely used for I/O interconnect in high-performance ceramic ball grid arrays (BGAs) and microchip modules (MCMs). For example, Intel`s Pentium II is put into plastic and ceramic BGAs and MCMs with flip-chip attach. The role of FC technology in addressing high-performance speed limitations is best seen in the development work of Alpine Microsystems (see "Alpine`s flip-chip and silicon-based interconnect" on p. 242).
Alpine`s flip-chip and silicon-based interconnect
As the speed of submicron VLSI ICs has reached unprecedented levels of performance, chip-to-chip interconnect speed has become the most significant system bottleneck that systems designers face. Alpine Microsystems (Campbell, CA) has invented a new microelectronic interconnect technology to eliminate this system design bottleneck. The company`s "Complex IC Technology" offers inter-chip speed and I/O bandwidth equal to single-chip solutions, yet at lower cost and higher levels of integration. This technology makes it possible to "package integrate" the fastest microprocessors, memory, and other state-of-the-art chips to create dense, high-performance "system-in-a-package" solutions - while using existing design, wafer fabrication, and assembly and test operations.
Briefly explained, Complex IC Technology integrates multiple ICs in a standard surface-mount package:
Probed wafers are electroplated, to precondition bonding pads for better adhesion, and then solder bumped.
After sawing, each individual die is mounted onto chip-size MicroPallet substrates, which are still in wafer form, forming a die-pallet subassembly. (Each MicroPallet substrate is a carrier for a single ICs and can be fully tested before proceeding to system-level integration; this is analogous to testing an IC in a package before attaching it to a board. Notably, this capability eliminates compound yield loss and the typical 2? cost premium for known good die.)
In a separate, parallel process, MicroBoard substrates are prepared for flip-chip assembly.
Chip-to-chip integration is accomplished when the diced die-pallet subassemblies are flip-mounted on the MicroBoard substrates (see figure).
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Alpine`s Complex IC Technology manufacturing flow is based on front-end and back-end flows similar to standard IC manufacturing.
Final assembly is into a BGA or QFP package.
Both the MicroPallet and MicroBoard are fabricated on silicon, thereby providing high-speed system-level signal routing like that possible with a system-on-a-chip design. Further, all MicroPallet and MicroBoard interconnect is patterned using semiconductor photolithography. The resulting routing density is greater than 2000 wires/in.
This packaging strategy has the advantages of single-chip integration, at vastly denser levels of integration, enabling highly integrated subsystems with form factor, performance, power and thermal management characteristics inherent in monolithic ICs.
The technology effectively extends manufacturable circuit sizes an order of magnitude higher than currently possible, yet at costs that increase linearly in proportion to the cumulative area of the integrated devices. Further, the technology allows integration of devices from dissimilar process technologies - logic, memory, analog, etc. - without combining incompatible semiconductor manufacturing processes. Potential cost-effective applications include microprocessors integrated with large cache memory, graphics controllers integrated with large DRAM frame buffer memory, and multiprocessor central processing units.
Such applications add to the growing opportunities forecast for FC technology (see Fig. 2). Forecasts are that by 2001 the number of chips requiring FC bumping will have increased to more than ~2.5 billion, representing a 35% CAGR over the next few years. Indeed, the industry is seeing a growing number of flip-chip foundries emerge. For example, Flip Chip Technologies (Phoenix, AZ), a joint venture of Delco Electronics and Kulicke & Soffa Industries, currently has the capacity to bump 20,000 wafers/week. The reliability of this technology is reflected in Flip Chip Technologies` claim of 6-s assembly yields with only 0.3-3 ppm defects.
Another growing-market-potential aspect of FC technology is that increasingly "1.0? flip-chip packages" (i.e., CSPs that are a true chip-size) are advantageous size and performance alternatives for "1.2?" class CSPs. Many experts contend that flip chip is the ultimate IC package solution, and its use for future high-performance and portable products is virtually guaranteed. A popular scenario is that CSPs are just stepping stones to FC-DCA; as CSPs are replacing SMT packages, FC allows systems manufacturers to reduce further the size and weight of products, and to design in more functionality. (Curiously, FC technology`s origins go back 30 years to IBM`s controlled collapse chip connection "C4" process. Another flip-chip technology that uses polymer bumps also traces its origins back a number of years (see "Polymer flip-chip technology").
Polymer flip-chip technology
With the accelerating role of flip chip (FC) technology in meeting the challenges of IC-to-board interconnect, established and patented polymer flip chip (PFC) bump technology is receiving increased attention. PFC has its roots in conductive epoxies for die attach, which have all but replaced eutectic bonding.
PFC technology uses polymeric conductor and dielectric materials, and fine-pitch screen printing and stencil techniques, to fabricate bumped ICs. The relatively simple process (see figure) is a totally additive technique in which wafers are first pattern-coated with a polymer dielectric layer using screen-printing; the screen printing leaves open contacts to the IC`s metallized I/O bond pads. Then, a stencil-printing technique applies isotropic silver-filled conductive bumps to the exposed bond pads. The bumps are then cured.
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The straightforward process sequence of polymer flip chip bumps compared to conventional solder bumps.
The process and equipment set - including fine-resolution screen printers with vision systems and automatic alignment, and inspection systems that determine crucially important bump coplanarity - has been developed by Polymer Flip Chip Corp. (Billerica, MA).
The dielectric coating serves as an alpha barrier over memory die, as a protective or passivation layer, or as a filter for photosensitive ICs. It can also be formulated to act as a thermally conductive heat sink on the surface of the chip. Although in many cases the dielectric coating improves the result obtained with the PFC process, it is not required for effective formation of the conductive bumps.
Once wafers are bumped and the bumps cured, they are diced and each individual die is tested. Board attachment is via a flip-chip aligner-bonder that places the bumps onto the board`s contact pads. Pressure and heat complete the mechanical and electrical connection. The attached chip does require an epoxy underfill and cure to strengthen the flip-chip assembly and provide environmental protection that eliminates corrosion or electrical migration. The low coefficient of thermal expansion of the underfill also provides dimensional stability to resist thermal shock.
Compared to solder-bump flip-chip processing, PFC`s advantages include:
lower capital equipment cost and fewer process steps,
low processing temperatures (<160?C), with the ability to bump to "low-temperature" substrates and rework MCM packages,
no lead (Pb), flux or CFC-containing solvents, and
A less brittle (more compliant) bump.
PFC can be applied to peripheral or area-array lead designs, using redistribution if required, and processing can be wafer-level or die-level.
Performance and reliability of solderless bump interconnects fabricated with the PFC process has been established with a variety of impressive qualifications that rival and in some applications improve on the reliability of solder bump, flip chips:
Contact resistance through 50-?m high conductive polymer bumps on gold has been repeatedly measured at <50 mW.
Ball shear data, generated by pushing 50-?m high, 110-?m bumps exceed 60 grams.
Thin-film gold-nichrome resistor circuits interconnected using conductive polymer bumps demonstrate electrical
stability comparable to gold wire beforeand after thermal shock and thermal cycle testing; here, the conductive polymer bumps exhibit 50% lower interconnect resistances than comparable devices fabricated with 1.0-mil gold wire.
High-frequency ICs have been fabricated using polymer bumps that operate at 18 GHz.
The inductance of polymer bumps is 0.1-0.02 nH.
The PFC process is applicable to a variety of applications. In particular, it is applicable in the growing market for smart cards, which today are all made with "chip-and-wire bonding" technology that includes a "glob-top" encapsulant. Here, the advantages of the PFC process include reducing process steps from seven to four, embedding larger chips in cards thereby increasing functionality, and eliminating the glob top for thinner cards. Most significant, PFC can be done for 50% less cost than chip-and-wire. Similarly, the PFC process is also ideally suited for radio frequency ID device applications.
FC pros and cons
FC-DCA achieves the shortest possible CSP die-to-board interconnect, thereby providing optimum inductance, capacitance, resistance, and speed values as well as improved signal propagation and noise isolation. In addition, a FC-DCA area array enhances power and ground distribution.
Because bumps can be placed anywhere on the FC interconnect surface, maximum I/O count is a function of area, not perimeter. In fact, area array FCs often mean an IC can be designed in less silicon real estate, enabling each wafer to produce more chips, which can increase fab capacity or decrease capital requirements.
Significantly, the disadvantages attributed to FC technology - handling fragility (particularly chip edges), the cost of bumping, and the need for underfill with a lengthy cure time - are progressively being solved as new technologies mature.
Flip Chip Technologies
One of the newest chip scale packaging FC-DCA technologies is Ultra CSP from Flip Chip Technologies. For each chip, when necessary, this wafer-level process first designs a redistribution route from the IC`s I/O pads to industry standard package pitches. It then fabricates CSP-size balls on the rerouted pads (Fig. 6), using a process that achieves ?1% alloy control and higher than conventional solder bumps; the strength of these balls means they do not require underfill. While Ultra CSP has passed the standard battery of reliability testing, the evolution of this process from proven "under the hood" Delco automotive applications speaks volumes; Delco has placed more than 15 billion solder joints in service with a 4-ppb failure rate.
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Figure 6. Flip Chip Technologies` wafer-level process fabricates CSP-size balls on the rerouted pads using a process that achieves ?1% alloy control and higher than conventional solder bumps.
Because I/O pitches are standard, the only design limits with Ultra CSP are the size of the die and the number of I/Os; for larger die with big I/O, there is a limit to the number of rows that can be redistributed.
Perhaps most significant in the whole arena of CSP alternatives, the cost of Ultra CSP comes in equivalent to a thin small outline package (TSOP) - around 0.7 cents per I/O in high volumes.
Conclusion
For most semiconductor manufacturers and their systems customers, the need to address the limitations of established SMT packaging technology is driven by some combination of packaging cost, system size, and system performance. Over the past few years, die-level 1.2?-CSP solutions have addressed these issues and provided attractive alternatives. But 1.2? CSP has also given IC suppliers greater vision of the ultimate in assembly and packaging technologies - wafer-level 1.0? FC-DCA. In reality, the future will probably see both 1.2? and 1.0? packaging solutions used to fill exploding market demands, particularly if a given technology provides industry standard I/O.
It seems, however, that wafer-level packaging technologies are the greater attraction for the future. While conventional semiconductor assembly will probably not be eliminated, at least in the near term, cost and time savings that come with wafer-level packaging - essentially putting semiconductor manufacturing`s back-end into the back of the front-end - will be too great to ignore.
Acknowledgments
The following are either trademarks or registered trademarks of the noted companies: PFC, Polymer Flip Chip Corp.; Complex IC Technology, MicroPallet, and MicroBoard, Alpine Microsystems; ShellPACK and Shell-BGA, ShellCase; Ultra CSP, Flip Chip Technologies; ChipScale BGA, Amkor Electronics.
PIETER "PETE" BURGGRAAF is a senior technical editor at Solid State Technology. He has 25 years of experience in the semiconductor industry, including work as a wafer-fab process engineer at Motorola and Siemens, capital-equipment customer-account specialist at ASM, and an independent writing consultant. Burggraaf has written over 200 feature articles on all facets of wafer fabrication and capital equipment application. He can be reached at 875 S. Yucca Drive, Wickenburg, AZ 85390; ph/fax 520/684-1265, e-mail [email protected].