NTRS critical-level lithography: Reading between the lines
07/01/1998
NTRS critical-level lithography: Reading between the lines
Syed A. Rizvi, Photronics Inc., Milpitas, California
Careful examination of the 1997 National Technology Roadmap for Semiconductors (NTRS) specifications for critical dimension and overlay tolerance reveals areas where the industry needs more detail and better definition of terminologies. This need is especially important considering that the time is at hand when the industry has to choose among the potential successors to optical lithography and begin the process of comparative evaluations so the applicable lithography methods are available for IC production in 2001.
The question before the industry is not "What are the lithography options for sub-0.15-?m technology?" Rather, it is, "Which options should we be pursuing?" Many believe that the sub-0.15-?m technology node, as defined by the 1997 NTRS, will lead to the post-optical era. For this there are five lithography contenders: x-ray, extreme ultra violet, electron projection lithography, ion-projection lithography, and direct write e-beam [1].
Some consider the extension of optical lithography beyond 0.15 ?m to be a possibility. The attraction is that it has a well-established infrastructure, and progress is likely to continue incrementally on a path that has only limited risks. This would require, among other things, innovations in maskmaking and clever processing and would not come without exorbitant costs.
It is time to make crucial decisions to narrow the various lithography options to a selected few. The Roadmap targets DRAM with 0.15-?m half-pitch on dense lines and 0.12-?m isolated lines on microprocessors (MPUs) shipping in 2001. Confidence runs high that by the year 2001, 193-nm ArF lithography will be ready to meet 0.15-?m demands. But will optical lithography deliver beyond 0.15 ?m?
The industry does not have the option of "given enough time and money anything is possible." For semiconductor manufacturing, progress in all disciplines must be fully synchronized and compatible. Late arrival of one technology will be of little value. Money and resources also become an issue if application of a technology becomes economically unfeasible, and pursuing it beyond a certain stage takes resources away from complementary technologies equally critical to IC manufacturing. Clearly, one industry task is universal agreement on the prioritization of process options, especially lithography options.
For the various nonoptical technologies, the difficult first challenge is narrowing the field to a select few for post-0.15-?m lithography. According to the 1997 NTRS, the "narrowing" should take place during 1998-1999, followed immediately by qualification and preproduction "shakedown" before being ready for the manufacturing floor. The industry is not even close to this narrowing point, however, and the norm is three to five years to commercialize a given process technology.
Narrowing the options
It seems advantageous that, in its narrowing, the industry should choose more than one lithography option, that is optical and one or two of the alternatives listed above. It should then apply the newer technology only to critical levels, a requirement driven by cost and equipment availability. Any new lithography technology with a limited infrastructure is likely to cost much more than a well-established technology. In addition, in early stages of application there will not be enough new tools on the market to meet industry demand.
With such a plan the industry will need a well-thought-out and comprehensive mix-and-match strategy that addresses overlay of consecutive layers and feature placement requirements, and avoids misrepresentations and ambiguities in characterizing new equipment and processes. The 1997 Roadmap, though, identifies overlay measurement as one of the most difficult challenges in the future of lithography. Experts acknowledge that overlay metrology has not kept up with advances in other areas of metrology. Here, then, we need a consensus on the interpretation of NTRS content, particularly that for lithography metrics.
Overlay, distortion, and feature placement
Traditionally, overlay metrology has been taken within the context of critical dimension (CD) metrology: A CD measurement is the distance between the two edges of some small feature, whereas overlay measurement is the distance between the centers of two features.
The basic premise of overlay measurement is based on superposition of patterns or "markers" from two different layers: A "box-in-a-box" is the simplest example. More complex patterns include a "box within a set of bars" or "one set of bars within another set of bars" (Fig. 1). The latter are often needed to improve a system`s capability to recognize and align to overlay patterns automatically.
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Figure 1. Overlay markers with varying degrees of complexity, from the simple "box-in-box" marker (top left) to the "multiple-set-of-bars" marker (bottom right).
With "box-in-a-box" measurements, the distance between the centers of two boxes patterned in two consecutive layers determines overlay; this is done by measuring the location of the edges of the two boxes. What makes it different from CD-metrology is that overlay is not a localized attribute like CD-metrology.
A CD measured at one location on a chip does not affect a CD at some other location of that chip. Overlay, on the other hand, measures the layout relationship between two layers over the entire chip; if the grids of the two layouts are not identical, different locations on the chip will exhibit different overlay values. An attempt to minimize overlay error at one location of a chip, by manipulating the relative positions of the two layers, can result in an increased error in another location on that chip. Overlay is thus a global property.
If the two layers in question are distorted and their distortions are identical, it may be possible to achieve perfect overlay between the two layers by simply matching features at a few locations. On the other hand, if the distortions of the two layers are different shapes or magnitudes, a perfect match over the entire area will never be obtained (Fig. 2). Therefore, we must view distortion with respect to feature locations as prescribed by IC layout design, rather than in relation to other layers.
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Figure 2. Examples of lithography distortion (left and right columns) compared to zero distortion (center). Even when the dots align, the distorted arrays do not. (Source: Interconnect Technologies, Mountain View, CA)
The 1997 NTRS specifications for overlay and feature placement (Table 1) are more lax than the same specification on the 1994 Roadmap [2]. While these "eased" values are somewhat surprising (typically, with advances in technology, critical parameters tend to become tighter), the values are still challenging and provide insight about lithography metrology needs and constraints associated with the "shakedown" of any new lithography technology. (It is also surprising that in the 1997 NTRS 1X specification, compared to 1994, tolerance did not move in the same direction as those for 4X, see Table 1).
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An overlay-measuring instrument must detect positions of four edges, two for the box on each layer, to determine a value for overlay between two layers. Thus, precision in locating the edge positions of the boxes (PEP) determines the precision in measuring overlays (POL). The relationship between PEP and POL values is complex, and they can differ from each other by 30-40%, depending on the type of markers used for measuring overlay [3]. This fact identifies a constraint on overlay measuring instruments in meeting requirements specified by the 1997 NTRS. We have seen little experimental verification, and certainly more study is necessary.
Feature placement and multipoint processing
While closely related to overlay, feature placement involves a different set of paradigms. An error in feature placement on a lithography mask may be caused by a system surge during pattern generation or by distortion in a lithography exposure system. In the first case, the error may be difficult to detect because it is random and localized. In the latter case, the error is systematic, thus readily discernible, and can be minimized by matching the distortion characteristic of all lithography systems used for processing a given chip. The effects of distortion appear as an error in image placement. Matching two systems that use similar imaging techniques is not as difficult as matching systems based on totally different principles (e.g., optical and e-beam projection). In the latter case, images on the wafer, which are characteristically identifiable, will reflect idiosyncrasies of two systems constructed with two different sets of principles. The measurement of the distortion characteristic of the two systems requires x-y coordinate measurement of features.
Determining feature placement precision also depends on measurement technique and data processing. It involves measuring the position of a feature within a coordinate system defined by x-y axes. Continued advances in coordinate-measuring instruments coupled with tighter specifications for feature position now require more comprehensive methods for defining the x-y axes of the coordinate systems used to measure feature positions. Specifically, defining a coordinate system requires selecting a minimum of two points from a pattern layout ("two-point processing"). Using more points ("multipoint processing") yields better precision in measuring feature placement.
The 1997 NTRS specifies that the measurement of feature placement be done using multipoint processing, which is quite understandable; but multipoint processing has characteristics of its own that must be taken into account. Results obtained from multipoint processing can vary, depending on the actual number of points taken into consideration, the area covered, and the density of points. These parameters need to be clearly specified when prescribing the multipoint approach.
It is not common knowledge that results obtained from multi-point processing can vary 20-30%, depending on the way the above parameters are chosen [5]. This is an important point that, if left unresolved, could lead to significant error in evaluations of next-generation lithography equipment. If the degree of detail sought here falls beyond the scope of NTRS, then it is up to the industry to come up with a standard format for carrying out multipoint processing of the data.
Any x-y coordinate measurement instrument used to determine feature placement would also need a more sophisticated calibration technique, perhaps using a self-calibration algorithm [6].
Minimum features
In addition to overlay and feature placement, NTRS specifications for minimum feature sizes and their qualification also need clarifying, to avoid misinterpretation and ambiguity in characterizing new lithography equipment and processes. Here, it is particularly important to distinguish between on-wafer and on-mask specifications. Seemingly, NTRS on-wafer minimum-feature specifications are given in more detail than on-mask specifications (Table 2). The NTRS gives mask specifications for isolated lines only, and not for other categories such as dense lines, contacts and development capability, as it does for wafers.
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For example, in the 2001 column of Table 2 the on-wafer minimum feature for isolated lines (microprocessor gates) is 120 nm. In the same column, the minimum mask feature is 480 nm, four times larger than the on-wafer specification. It is obvious that 480 nm refers only to isolated lines on mask, even though the NTRS labels it "mask minimum feature."
The NTRS lists three other on-wafer minimum feature categories: dense lines at 150 nm, contacts at 170 nm, and development capability at 100 nm. But these categories are not specified for masks. Does this mean that a "four times larger" rule can be applied to these three categories when specifying minimum mask specifications? Rather than leave such an important point to interpretation, it would have been better to state clearly the appropriate mask minimum features for lines, contacts, and development capabilities; or, if the intent was brevity, a comment like "minimum mask CD specification equals four times minimum wafer CD specification" would be appropriate.
On the other hand the CD-qualifications (i.e., CD tolerance, CD uniformity, mean-to-target values, and CD linearity) are well specified for masks, but lack details for wafers. It may have been assumed that mask uniformity will replicate itself on wafers, but this assumption is valid only if exposure-source intensity variation over the chip area, resist-thickness variation, and surface topography do not play any role in CD uniformity - an assumption that is questionable.
Conventionally, the industry has specified CD tolerances to vary within a given percentage (typically 10%) of their value and has attributed a portion of this percentage (also typically 10%) to specify precision of the measuring instrument. The 1997 NTRS seems to have followed this convention for wafers; for 2001 the tolerance for a 120-nm gate CD is specified as 12 nm (i.e., 10%) with 2 nm (i.e., 17% of 12 nm, rather than 10%) attributed to 3-s instrument precision.
Applying the "typical 10% and 10% convention" to mask specifications for 2001, 3-s precision given to measuring instruments for 480-nm features would be 4.8 nm (i.e., 10% of 10% of 480 nm). The NTRS, however, uses a different convention when dealing with masks; it replaces CD tolerance with "CD-uniformity" and "mean-to-target" values. For example, with the 2001 target value of 480 nm, the specification for "mean to target" is 10 nm, which simply states that the mean of all readings on the chip must remain within the bounds of 470 and 490 nm or ?2.1% of the 480-nm targeted value. This specification is then supplemented by a uniformity specification that all features must fall between ?8 nm of the mean value, where the mean value is constrained within 470-490 nm. This amounts to a CD tolerance of 1.6-1.7%. The point is not that features can or cannot be controlled to this tolerance in the stated range; rather, it is important to have a clear perspective of these numbers when trying to meet lithography challenges.
As a rule of thumb, 3-s precision of measuring instruments is typically specified at 10% of CD tolerance. If we apply this rule to the discussion above, we would need a measuring instrument with a 3-s precision of 0.16-0.17% of the feature width, or 8 ?. Equipment manufacturers certainly need to address the reality of instruments with such precision.
The 1997 NTRS also specifies CD linearity for masks, but not on wafers. This may be fine if the mask is the only place where linearity is an issue, but this assumption is valid only if there are no contributions to linearity from the lithography system or processing, something that we have to validate when developing the selected new lithography technologies. Most important, the industry needs to define "linearity," because today there is no consensus.
It is also important that the various specifications associated with minimum features, as discussed above, must be qualified for the number of measured points and the entire area over which the measurements are made. This is required to give statistical validity to the final measured values.
Finally, the 1997 NTRS shows that on 1? masks, the optical proximity correction (OPC) value is the same as the minimum feature. This implies that we must create minimum printable features and expect them not to print, but act only as OPC. This is difficult to conceive, let alone perform.
Equipment availability on NTRS timeline
Constraints from the precision of measuring instruments and the availability of next-generation lithography systems play important roles as we travel down the Roadmap. For example, the previously discussed 8 ?, 3-s precision instrument is needed to meet CD control specification in 2001. This means that the decision to select the next generation of lithography equipment cannot be made with full intelligence without involving equipment manufacturers, who in the past have made significant contributions to keep the industry tracking on the curve of Moore`s Law. (Dr. Moore himself said his "law" would not have been possible without the gains made by the semiconductor equipment industry [7].)
Until recently, equipment advances have been piecemeal - incremental changes in existing technologies that pose no major risk when introduced on the manufacturing floor. Now, as the industry explores new equipment territory, it faces quite a few nonincremental options with little data about manufacturing effectiveness. Most of these options are in early stages of development and will require industry support and interest to achieve commercialization. We should not expect equipment manufacturers to invest resources on product development for which there will be no potential buyers.
It may take even longer than the typical three to five years for commercial equipment development if the technology is quite new and has little or no infrastructure to support it. In addition, the industry`s challenge to ship 0.15-?m, half-pitch DRAMs and 0.12-?m-gate MPUs by 2001 will coincide with introducing next-generation mask sizes and 300-mm wafers. Both will bring about a multitude of issues in and of themselves, such as mechanical precision and handling, which will concern IC manufacturers.
Most wafer-processing systems must be retooled to accommodate larger wafers and masks, while maintaining process uniformity and repeatability. This is going to be a demanding task for equipment suppliers and users. These two groups must work as partners to develop the required next generation of equipment.
Crucial to this cooperation is that equipment suppliers and users seriously consider the task of narrowing equipment set options through cost analysis, sophisticated modeling, and critical evaluation of systems and the required infrastructure. Such "narrowing" decisions, however, must be unbiased and avoid the classic "not invented here" syndrome.
Minimum features no panacea
A striking characteristic of the Roadmap is that its timeline is synchronized with the minimum features for a specific technology node. Thus, the Roadmap depicts minimum features as a means for gauging the performance of the IC industry. This may be true today and in the immediate future, but shrinking features will soon reach a point of diminishing returns. As semiconductor devices continue to shrink, performance becomes less dependent on transistor switching speed and more dependent on interconnect conductivity, where reduced interconnect pitch can result in increased interconnect RC delay.
Alternatives to feature scaling, such as low-k interlayer dielectrics and high-conductivity metals, are already being explored. It is appropriate that some of the concerns about lithography could be shared by those working on interconnect technology. Lithography then can focus on other critical areas where it can make significant impacts on IC technology.
Other lithography challenges
Today, the challenge in lithography is to focus on improving and perfecting state-of-the-art technologies; for example, improving gate uniformity, rather than just trying to make smaller features. John Sturtevant of Motorola has estimated that 1 nm in a gate-channel CD could improve chip speed by 1 MHz and increase chip price by $7.50 [8]. Interestingly, this represents a CD control of ?8% instead of the conventional ?10%.
As explained earlier in this article, overlay improvement is a critical area that must be seriously addressed if mix and match is to play a major role in the future of lithography.
In another area, verification of OPCs and phase-shift masks - both designed to compensate for on-wafer process and optical characteristics - is difficult without printing onto a wafer. Developing methodologies to evaluate these technologies without printing is another great challenge for the industry.
Conclusion
There is a need for well-articulated and unified definitions and terminology used in the 1997 NTRS, especially for lithography performance. It is crucially important that the industry work on these needs as it finalizes the decision on which emerging lithography options to pursue. To be successful with tomorrow`s semiconductor manufacturing technology, all members of the industry must speak the same language to avoid ambiguities.
Acknowledgments
The author thanks his managers, Alex Naderi and Doug Vandenbroeke, for allowing time and resources for writing this article; his colleague Kent Nakagawa, and Shahzad Akbar for reviewing the manuscript and providing constructive input; Asim Husain of Intel Corp. for taking time to discuss issues and challenges in interconnect technology.
References
1. The National Technology Roadmap for Semiconductors 1997, Semiconductor Industry Association.
2. The National Technology Roadmap for Semiconductors 1994, Semiconductor Industry Association.
3. S. Rizvi, "Analyzing the Tolerance and Controls on CD and Overlays as Prescribed by the NTRS," SPIE Symposium on Microlithographic Techniques in IC Fabrication (Singapore), Invited Paper, 3183-25, June 25-26, 1997.
4. S. Rizvi, "Metrology of Registration," paper presented at SEMICON EUROPA, Zurich, Switzerland. March, 1990.
5. S. Rizvi, "Feature Placement and Two Dimensional Metrology" (to be published).
6. M. Raugh, S. Rizvi, "Improving Overlays by Self-Calibration in Position Metrology," First International Workshop on Statistical Metrology, Honolulu, June 9, 1996.
7. G.D. Hutcheson, "Ten trends shaping the next 10 years," Solid State Technology, Volume 40, No. 5, p. 67, 1997.
8. J. Sturtevant, et al., "CD Control Challenges for Sub-0.25 ?m Patterning," SEMATECH DUV Lithography Workshop, Austin, TX, October 16-18, 1996.
SYED A. RIZVI received his MS degree in physics from Northeastern University, Boston. He has more than 25 years of experience in the semiconductor industry, mostly with Texas Instruments. Prior to joining Photronics, he managed university research programs at SEMATECH and SRC, where he was an assignee from TI. He has authored numerous publications on metrology and lithography and has co- authored two books on VLSI technology. Rizvi is a senior staff scientist at Photronics Inc. 1982 Tarob Ct., Milpitas, CA 95035; ph 408/262-8800, fax 408/263-3228.