RTP technology for tomorrow
06/01/1998
RTP technology for tomorrow
R.P.S. Thakur, P.J. Timans, S.P. Tay, AG Associates Inc., San Jose, California
Current trends in the semiconductor industry influencing the future of RTP technology include the migration to smaller device geometries, new materials, thinner films, shallower junctions, and large aspect ratios on larger-diameter wafers. RTP technology offers a controlled, transient, and ultraclean environment for thermally activated processes that are increasingly difficult to achieve in a batch furnace. The advances made in this field have helped in critical areas such as defect reduction, yield enhancement, cycle-time reduction, and reduced thermal budget processing. New generations of RTP equipment incorporate sophisticated hardware developments, which provide excellent thermal control for both 200- and 300-mm wafer sizes.
In this article, we will discuss the evolution of a new generation of RTP technology from three perspectives. First, we will focus on the requirements for advanced RTP applications, which are driving the need for tighter tolerances in hardware design. Then we will discuss design, simulation, and development of a new RTP system, focusing on the basic physics underlying the hardware configuration. Simulations using finite element heat-transfer models illustrate that the new design provides temperature uniformity better than 2?C (3-s variation). Temperature uniformity is controlled using multiple sensors and a dynamic temperature distribution control algorithm. Last, we will confirm the system`s capability through experimentation, presenting the results for rapid thermal oxidation (RTO) and silicide formation in the new system. We will also demonstrate the ability of the hardware supporting novel RTP applications, including low-temperature processes and high-ramp-rate anneals.
RTP technology improves revenue generation in the IC industry and also helps to extend Moore`s Law [1] well into the next decade. The current applications of RTP in manufacturing include silicide anneals, implant and other dopant activation, borophosphosilicate glass reflow, rapid thermal nitridation, hardened oxides, reoxidation, and implant and diffusion monitors [2]. Advances in RTP chamber design, temperature control and uniformity, ambient availability, and the use of various resistive- and lamp-heating systems by different vendors have helped provide solutions that comply with SIA Roadmap requirements.
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Figure 1. Process performance of Heatpulse 8800 using a ceramic shield for enhanced uniformity heating and temperature control. The RTO process took place at 1100?C for 30 sec, with a ramp rate of 50?C/sec. The mean oxide thickness changed by <1 ? over 240 wafers. Mean oxide thickness = 85.5 ?; repeatability = 0.6%; uniformity (1 s) = 1.1%; and sensitivity = 0.65 ?/?C.
Industry drivers for new tool development
Like any evolving technology, adoption of a new RTP system design requires significant technical and financial resources by vendors. The three major challenges involved in RTP development are:
1. Equipment manufacturers must deliver high-productivity tools with improved reliability and lower cost of ownership.
2. Equipment companies must work on process solutions to accelerate device development by customers, either through collaboration with customers or independently.
3. Device makers must provide timely feedback to vendors so that desired equipment improvements are incorporated and tested before the equipment goes into manufacturing.
New device architectures and materials are the main factors that make RTP and its derivatives, such as RTP-assisted chemical vapor deposition (CVD) and cluster processing, critical technologies in the industry.
Advances in wafer temperature control lie at the heart of the improvements for RTP technology. The problem of temperature control can be split into three separate components: uniformity within the wafer; repeatability on different wafers of the same kind; and repeatability among wafers of arbitrary types, which may have markedly different optical properties. The total components of variation (TCV) refer to the combined standard deviation in temperature control arising from these factors.
In the 1997 SIA Roadmap [3], the thermal/thin-film process requirements for 0.18-?m technology include a gate oxide equivalent thickness of 3-4 nm and a 3-s variation in thickness control of ?4%. In terms of temperature control, this translates to a TCV of ?3?C. This TCV applies, in general, to all other thermal/thin film processes, such as implant anneal, activation, and the silicide formation process. The target junction depth of 70 nm requires excellent temperature control and high ramp rates (up to 400?C/sec) to minimize diffusion effects [4].
Figure 1 shows the uniformity and repeatability of a RTO process in an AG Associates` Heatpulse 8800 with ceramic shield. By analyzing the sensitivity of the oxide thickness to temperature, we can show that the results are equivalent to a 3-s TCV of 4.9?C, indicating excellent temperature control for the current generation of processes in manufacturing. Nevertheless, the RTP tools require redesign and development to meet the stringent specs for =0.18-?m processes.
In addition to temperature control, several other factors have to be considered in the redesign. First, the system has to accommodate the use of new processing ambients, including reactive gases, that may undergo complex chemical reactions with the wafer [5]. Second, in manufacturing, the deployment of advanced salicide RTP processes, including cobalt silicide, requires fast purges to minimize residual oxygen concentration [6]. Finally, the first silicide RTP temperature to form cobalt salicide is approximately 500?C, so the system`s pyrometer must be able to measure low temperatures accurately
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Figure 2. Comparison between a) a 0.25-?m RTP system configuration and b) an advanced design addressing 0.18-?m process requirements.
System design for high-process uniformity and ramp rate
The first challenge in wafer temperature control lies in maximizing the uniformity of temperature distribution on any particular wafer. In the steady-state portion of a heating cycle, this uniformity depends on how the balance between radiant power delivered and thermal losses varies across the wafer. Variations in the power delivered arise from the configuration of the heating lamps and the geometry of the reaction chamber. Patterns on the wafer can introduce spatial variations of the power absorbed.
Geometric factors and wafer patterns also create spatial variations in the power loss. For example, the edge of the wafer tends to lose more heat than the center because of its geometry and convective heat loss effects.
Thermal conduction within the wafer tends to smooth out the temperature profile, reducing nonuniformity. The shorter the length scale on the wafer, the stronger the effect of smoothing.
The high thermal conductivity of silicon guarantees uniformity at millimeter-length scales, but keeping the same temperature uniformity over a 10-cm range is much more challenging. There is effectively no temperature profile smoothing from thermal conduction, and the extremities of the region act as if they are different wafers whose temperatures are defined by the local values for the power absorbed and emitted.
Using the Stefan-Boltzmann law for thermal radiation, the power balance on the wafer is
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where h is a local power-coupling constant, P is the local incident power density, sSB is the Stefan-Boltzmann constant, T is the local wafer temperature (in Kelvin), and Heff describes the efficiency with which power is lost by thermal radiation. Heff includes the possibility of loss from both sides of the wafer and the effect of re-reflection of the emitted radiation back onto the surface. Eqn. 1 can be used to determine the sensitivity of wafer temperature to fluctuations in P, h, and Heff. For fluctuations
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Figure 3. Simulation of the temperature uniformity predicted for two multizone illumination schemes in the Starfire system. Simulation helps optimize the heater layout, reducing the total range of temperature deviation from 3.3?C to 2.3?C.
?P, ?h, and ?Heff, the corresponding temperature fluctuation ?T is
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This equation shows that variations in incident power, power coupling, and heat loss are all equally significant to temperature disturbance. A 1% change in the incident power can produce a 0.25% change in the absolute temperature of the wafer. For a wafer at 1100?C, a 1% change in power density would change the wafer temperature by 0.0025 ? 1373 K = 3.4 K. This example illustrates the formidable technical challenge to control the 3-s wafer temperature uniformity to ~1?C.
One of the main practical consequences is the need for a carefully designed lamp-heating array. The problem of designing a suitable heater is not the same as that of designing a very uniform illuminator. Uniformity optimization requires controllability as well as uniformity. Controllability allows one to affect the power delivery to selected regions of a wafer relative to others, for example, to counteract nonuniformity in the heat-loss distribution. A heater with a multizone structure to fine tune the illumination profile can provide uniformity despite the varying power delivery requirements of different types of recipes and heat-transfer conditions that arise from the use of different types of wafers, gases, and gas flow rates.
Traditional RTP systems use a rectangular reaction chamber combined with linear lamp arrays (Fig. 2a), with different groups of lamps gathered together as zones, whose relative power settings can be adjusted to provide wafer temperature uniformity. Figure 1 shows that this approach provides a 3-s TCV
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Figure 4. a) Process result of RTO in the Starfire system on a 200-mm wafer. The RTO process conditions were 1150?C for 30 sec with a ramp rate of 75?C/sec. A 49-point measurement showed a mean thickness of 125.0 ? and a 1-s standard deviation of 0.31% or 0.39 ?. The total range of thickness was 2.0 ?; the contour interval was 0.54%; and sensitivity was 0.75 ?/?C. b) Using a sensitivity curve, a 0.75 ?/?C conversion factor was applied to uniformity performance to deduce 1 s of 0.5?C uniformity up to 3 mm from wafer edge.
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Figure 5. Starfire 300 RTO performance on a 300-mm wafer. The ramp rate was set intentionally high at 100?C/sec. A 121-point measurement showed a mean thickness of 77.5 ? and a 1-s standard deviation of 1.1% or 0.83 ?, indicating 1.1?C uniformity up to 3 mm from wafer edge, for a 0.72 ?/?C conversion factor.
Wafer rotation is important because it smoothes out local imbalances of power delivery and loss that cause temperature nonuniformity. For example, one region of the chamber wall can have a lower reflectivity than the rest as a result of a feature, such as a wafer-loading port. If the wafer is static, there will be less re-reflection of radiation onto the part of the wafer near the feature, increasing Heff in Eqn. 1 and causing a local drop in temperature. Rotation can attenuate and axis-symmetrize the effects of azimuthal nonuniformity in lamp illumination profiles and other heat-transfer effects. For a rotating wafer, the effect is spread out over the entire wafer at that radius, greatly reducing the magnitude of the temperature depression and turning the residual nonuniformity into a radial profile. Adjusting the lamp-zone powers can tune out this effect. In a linear lamp RTP system, the wafer geometry does not match that of the lamps or the chamber, limiting the degree of uniformity tuning that is possible, especially for a rotating wafer. As the wafer rotates under a linear lamp, the illumination profile of the lamp is swept out over a very large area of the wafer, making it difficult to tune out radial temperature nonuniformities with length scales of only a few centimeters. An axisymmetric heater structure, where the zones match the symmetry of the wafer and the rotation, overcomes this problem.
The design of an axisymmetric lamp array also poses challenges to the delivery of the required uniformity and controllability, while maintaining efficiency in power delivery to permit high-ramp-rate heating. The heater in Figure 2b was designed using optical techniques; sophisticated heat-transfer models; and experimental studies of illumination profiles, wafer temperature response, and process results. The optical design configuration used ray-tracing models to predict the lamp-zone illumination profiles and power transfer efficiency. The predictions were validated on test fixtures that measure the illumination profile at the wafer.
After establishing these profiles, we used finite element, heat-transfer models to evaluate the consequences for wafer temperature uniformity and lamp power requirements. Figure 3 illustrates the temperature uniformity expected for two multizone illumination schemes that we assessed during the development of the new 200-mm system. The rapid comparison of the temperature profiles predicted for many different potential designs allowed optimization of the lamp-heating array before construction of a real heater assembly. For the examples shown, adjustments in the heater layout reduced the total range in the predicted temperature on a 200-mm wafer from 3.3?C to 2.3?C. The system capability is well within the expected requirements for 0.13-?m technology.
We took a similar design approach for the 300-mm heater design, using a more complex model of the system to make the thermal predictions, including a 2-D finite element model developed in collaboration with Sandia National Laboratory, Livermore, CA. When the simulations indicated that the desired heater performance could be attained, the final stage of the development involved constructing full-scale test heaters, running process wafers, and optimizing the lamp-zone settings to obtain good process uniformity (Figs. 4, 5). Figure 4a is an RTO wafer map showing a 49-point measurement of oxide thickness on a 200-mm wafer with 3-mm edge exclusion. The RTO processes were carried out in AG Associates` Starfire system at 1150?C for 30 sec, with a ramp rate of 75?C/sec. The mean thickness is 125.0 ? and the standard deviation (s) is 0.31% or 0.39 ?. Figure 4b is a plot of oxide thickness against oxidation temperatures, which gives a sensitivity of 0.75 ?/?C at 1150?C. This sensitivity means that the standard deviation of 0.39 ? is equivalent to 0.52?C. The RTO wafer map in Fig. 5 shows a 121-point measurement of oxide thickness on a 300-mm wafer with 3-mm edge exclusion. The RTO was performed in the Starfire 300 system at 1100?C for 30 sec, with a ramp rate of 100?C/sec. The mean thickness is 77.5 ? and the standard deviation is 1.1%, or 0.83 ?. The sensitivity is 0.72 ?/?C at 1100?C, so this standard deviation is equivalent to 1.1?C. The 3-s temperature uniformity for the RTO processes used to test the systems is, therefore, ?1.5?C on the 200-mm system and ?3.5?C on the 300-mm system.
One interesting challenge facing RTP equipment designers arises from the increasing need to provide very high-ramp-rate heating to minimize the effects of transient-enhanced diffusion during ion-implantation damage annealing. This requirement means that the heater system must simultaneously achieve very high-power delivery efficiency and high-temperature uniformity. We included this design constraint in the 300-mm development program, allowing the system to ramp a 300-mm wafer to 1100?C at a constant ramp rate of 150?C/sec. The constant ramp rate is significant, because the peak power demand occurs just at the point immediately before the wafer is at steady state. Tailoring the ramp profile to obtain higher ramp rates at lower temperatures is possible, but may not be appropriate for minimization of thermal budget. The high-power delivery efficiency of the heater, coupled with the fast control action of a 50-Hz control loop, allows high ramp rates, even to the highest process temperatures needed for RTP.
Advances in temperature measurement and control
Temperature repeatability is largely determined by the effectiveness of the closed-loop control of wafer temperature. In earlier generations of RTP equipment, application of closed-loop control used feedback from a pyrometer that only viewed one part of the wafer. The ratio of the power delivered to any lamp zone was fixed in each block of a processing recipe and the zones were "slaved" together to respond to the feedback signal. Since lateral thermal coupling through thermal conduction only extends a few centimeters from the control point, the rest of the wafer was not directly under closed-loop control. This required very stable power delivery to those parts of the wafer with respect to that delivered at the control point. Careful hardware design in current RTP systems allows very repeatable operation, even with this limitation, largely as a result of high-stability lamp power supplies and careful operating procedures. The need for even tighter temperature control, however, makes this approach impractical when repeatability (3 s) has to be <0.5?C. Using multiple temperature sensors to observe the wafer at several radii and provide feedback to a multiple-input, multiple-output (MIMO) control algorithm can dynamically control the lamp-zone powers to keep the observed temperatures on track. MIMO control is a powerful weapon in improving repeatability, since the automatic uniformity tuning allows the system to compensate for subtle changes in heat-transfer conditions associated with different recipes and wafers, or by aging of components in the chamber or heater. MIMO control also maintains temperature uniformity during the whole heating cycle, including the ramps up and down. Dynamic temperature control ensures better process uniformity and minimizes the risk of inducing slip on larger-diameter wafers heated to high temperatures at high ramp rates.
Each temperature sensor channel must exhibit high-temperature resolution and stability. For the new system, a special, new type of pyrometer samples radiation from several positions on the wafer via a network of fiber-optic cables. It provides temperature readings 50 times/sec for each channel to permit dynamic control at high ramp rates. Figure 6 shows a theoretical prediction of the pyrometer`s 3-s noise performance, which imposes the ultimate limit on repeatability. This performance has been confirmed through experiments. The experimental temperature resolution is <0.5?C, even at temperatures as low as 350?C, where weak thermal radiation creates the greatest signal-to-noise problem. Fig. 6b shows a temperature-time recording for a wafer processed under closed-loop control at 400?C, illustrating the system`s ability to handle important new low-temperature processes, including the formation of cobalt salicides.
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Figure 6. a) A theoretical curve showing the Starfire pyrometer`s 3-s noise performance at the low-temperature range, and b) a temperature-time recording for a wafer being processed under closed-loop control at 4008C.
Figure 7 shows the low-temperature capability demonstrated in the process results . A new CoSi2 RTP process using TiN capping produces lower sheet resistance (Rs) and tighter sheet resistance distribution than the conventional cobalt salicide process [7]. In our experiment, the cap process used 30 nm of TiN over 10 nm of cobalt metal to protect cobalt from oxidation after deposition and during first rapid thermal silicide formation (RTS1) in the 480-520?C temperature range. After the RTS1, a SC1(NH4OH:H2O2:DIH2O = 1:1:5) solution etched off the TiN cap. The second rapid thermal silicide formation (RTS2) at 700?C converted CoSi to CoSi2. Figure 7a shows the uniformity and repeatability results for a cassette of TiN/Co wafers annealed at 500?C for 30 sec in nitrogen (RTS1). For both Co (10 nm) and TiN/Co (30 nm/10 nm) wafers, we observed consistent uniformity of 2-3% (1 s) for the first anneal. The pre-map mean Rs and the 1-s uniformity for the TiN/Co are consistently 15 ?/sq. and 5%, respectively. The pre-map and post-map were all measured with 6-mm edge exclusion. The sensitivity factor for the TiN/Co silicide formation was 0.093 ?/sq./?C. We measured the sheet resistance for the TiN/Co wafers after the complete removal of the TiN cap layer by the SC1 etch at 75?C. For the four TiN/Co wafers, the average of the mean Rs values is 96.5 ?/sq. and the total range is 0.73 ?/sq., suggesting an equivalent 3-s repeatability of ~0.38%. Figure 7b shows the uniformity and repeatability results for a cassette of TiN/Co wafers annealed at 700?C for 30 sec in nitrogen (RTS2). The mean values of the sheet resistance after RTS2 for the four wafers are 5.03, 5.03, 5.03, and 5.05 ?/sq. The corresponding 1-s uniformities are 3.25%, 3.23%, 3.21%, and 3.24%. The total range in Rs is 0.02 ?/sq., suggesting an equivalent 3-s repeatability of ~0.2%.
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Figure 7. a) High-performance process results in the very low-temperature range demonstrated through cobalt silicide reaction (RTS1). Overall repeatability is 0.4% for 500?C, 30-sec anneal cycle in nitrogen. Average of means = 96.50 W/sq., max.-min. = 0.73 ?/sq., repeatability = 0.38%. b) High-performance process results in the medium temperature range demonstrated through cobalt silicide reaction (RTS2). Overall repeatability is 0.2% for 700?C, 30-sec anneal cycle in nitrogen. Average of means = 5.035 ?/sq., max.-min. = 0.02 ?/sq., repeatability = 0.2%.
The final element in the temperature control problem arises from temperature measurements of wafers with radically different optical properties. One of the problems with early RTP systems stemmed from the systems` inability to process wafers with different backside coatings without recalibration to correct for the impact of the coatings on pyrometer control of wafer temperature. Several approaches developed over the last few years have greatly reduced the scale of this problem [8]. These include the use of ceramic shield technology, which virtually eliminates the effect of wafer backside coatings on temperature control [9].
Other developments in pyrometry, including a sophisticated implementation of the use of an auxiliary reflector to create a virtual black body cavity, have been incorporated into the advanced system to provide excellent emissivity independence.
Conclusion
In this article, we discussed the evolution of a new generation of RTP technology by deriving the requirements of the new RTP system from the given generation of technology, and then focusing on the basic physics underlying the hardware configuration. Simulation using finite element heat-transfer models showed that the new design provides temperature uniformity better than 2?C (3-s variation). We confirmed the system`s capability through experimentation by presenting the results for RTO and silicide formation. We also demonstrated the ability of the hardware to support novel RTP applications, including low-temperature processes and high-ramp-rate anneals. Flexibility in the new RTP system becomes a key feature to address the needs of several IC generations. The new system, with its modular design, has the flexibility of clustering with various clean and CVD modules. n
References
1. R.P.S. Thakur et al., "Process Simplification in DRAM Manufacturing," IEEE Transactions on Electron Devices, Vol. 45, No. 3, p. 609, 1998.
2. R.P.S. Thakur, "Rapid Thermal Processing and ULSI Electronics," in Semiconductor Fabtech, 5th ed., p. 261, 1996.
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5. S.P. Tay, Y.Z. Hu, Y. Wasserman, "Manufacturability of Rapid Thermal N2O Oxynitridation for Ultrathin Gate Dielectrics in 0.25-?m CMOS Processes and Beyond," Proceedings, 5th International Conference on Advanced Thermal Processing of Semiconductors (RTP `97), pp.129-134, 1997.
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7. Q.F. Wang et al., "Manufacturability Issues for Application of Silicides in 0.25-?m CMOS Processes and Beyond," Mat. Res. Soc. Symp. Proc., Vol. 402, pp. 221-231, 1995.
8. P.J. Timans, "Temperature Measurement in Rapid Thermal Processing," Solid State Technology, Vol. 40, p. 63, 1997.
9. P.J. Timans, R.N. Morishige, Y. Wasserman, "Emissivity-independent Rapid Thermal Processing Using Radiation Shields," Mat. Res. Soc. Symp. Proc., Vol. 470, p. 57, 1997.
R.P.S. THAKUR received his BS degree in electronics and communication engineering, and MS and PhD degrees in electrical engineering. He is AG Associates` VP of technology and R&D. He holds more than 35 patents with several dozen more pending, and has authored nearly 130 papers in journals and conference proceedings. AG Associates Inc., 4425 Fortran Drive, San Jose, CA 95134-2300; ph 408/935-2000, fax 408/935-2700.
P.J. TIMANS received his PhD degree in electrical engineering and was a research fellow at the Cavendish Laboratory, Cambridge University, UK, where he studied the thermal radiative properties of semiconductors and in situ monitoring of RTP processes. He is director of R&D at AG Associates, focusing on temperature measurement and control in RTP.
S.P. TAY received his PhD degree from the University of Salford, UK. He has managed the process development department at AG Associates since 1995, and specializes in front-end silicon processing, with emphasis on oxidation and diffusion. Tay has authored more than 50 technical papers, and has been granted 12 patents in semiconductor technology.