Copper plus low-k damascene built at TI
06/01/1998
Copper plus low-k damascene built at TI
Texas Instruments (TI), Dallas, TX, has announced a viable copper wiring technology for IC fabrication. TI joins the ranks of IBM and Motorola, which have both made early introduction of "copper technology" a marketing buzz as well as a key to the future of ICs.
The twist: TI is the first semiconductor manufacturer announcing integration of copper interconnects and an ultra-low dielectric constant (low-k) material dubbed xerogel, both used in a damascene architecture (see figure). This combination was quietly revealed in a late-news paper at the IEDM in December and formerly announced March 18 at TI`s Kilby Center, where a team of R&D engineers developed and continue to work on the copper process for 0.15-?m technology and beyond.
The Kilby Center is a 50,000-ft2 Class 1 wafer fabrication facility dedicated to fast cycle time development of =0.15-?m process technology in support of TI`s logic, mixed signal, and memory products.
Robert Havemann, TI fellow and manager of interconnect development, said, "We looked at the combination of copper and low-k dielectric as the supreme challenge in interconnect trends because it addresses resistance and capacitance issues as well as reducing interconnect levels." He emphasized that the new process is not yet in production, but is a front-running candidate for TI, and even the industry, because it clearly addresses interconnect capacitance issues that dominate performance for sub-0.15-?m spacing. Havemann expects ICs with copper technology to ship in 1999.
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SEM showing the excellent gap-filling characteristics into 0.15?m 6:1 aspect trenches of TI xerogel dielectric.
(Courtesy of TI)
Simultaneously, AlliedSignal Electronic Materials (ASEM), Sunnyvale, CA, identified TI`s xerogel precursor as its Nanoglass product. The commercial availability of Nanoglass and TI`s propensity to cross-license intellectual property seemingly puts the low-k side of the process on the open market. Neil Hendricks, ASEM technology development manager, noted, "AlliedSignal has been working on low-k materials issues since 1993."
TI`s xerogel seems ideal for an interlayer dielectric (ILD) through multiple IC generations. It is a microporous network of silica with high thermal stability and a low thermal-expansion coefficient. Most significantly, its porosity can be tuned in the deposition process to deliver a k from near 1 to 3. In the reported work, TI engineers used xerogel with a dielectric constant of 1.8 and a porosity of approximately 75% to build prototype chips.
Changming Jin, a member of TI`s technical staff, commented, "The ability to tune the porosity of xerogel provides us with a single-material approach to cover the whole spectrum of dielectric constant needs outlined in the SIA Roadmap, reducing repetitive process development time."
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The TI process starts with a xerogel-adhesion layer-oxide stack deposited on oxide. Slightly modified commercial spin-track systems perform the xerogel spin-on. Phase-shifted i-line lithography patterns 0.3-?m trenches that are etched in a single RIE step (the xerogel provides a strong endpoint trace and a 3:1 selectivity to the underlying oxide). The process lines the trenches with a PVD Ti-TiN diffusion-barrier layer - TI evaluated this with and without an oxide sidewall - and a PVD copper seed layer before copper electroplating. CMP removes copper from the field with minimal oxide loss and copper dishing. The final cap, through which bond pads are opened, is a silicon nitride-oxide-silicon nitride stack. The resulting copper trench thickness is 0.6 ?m.
The TI team clearly notes that the material technology behind xerogel is leading "equipment challenges" in 0.15-?m device technology. Havemann commented, "Lithography continues to pace scaling. In addition, our combination of copper and low-k dielectrics requires further CMP process and equipment development.
Hendricks noted, "Continued process development, including CMP performance testing, scaled back SiO2 etch chemistry concentrations, adhesion testing, and thermal desorption studies, are part of joint development projects underway at other industry leaders, while AlliedSignal is scaling up precursor production."
Eden Zielinski, a member of TI`s technical staff, reported, "The resistance of our copper-xerogel damascene structure, with and without the oxide sidewall, is 30% and 28% lower than that of an equivalent conventional aluminum-based structure (see table). Similarly, capacitance is 14% and 5% lower. Looking at it another way," she said, "capacitance for an aluminum-oxide structure with the same resistance as the copper-xerogel structure would be 29% higher and would correspond to a metal stack height of 0.96 ?m, a 3.2:1 aspect ratio." While the oxide trench liner increases resistance and lowers capacitance, it does reduce leakage current "outliers."
Havemann said, "While lowering resistance with copper solves a near-term problem, we think reducing the capacitance effect is a more critical issue because unless that problem is solved, chip performance, power, and operating voltage will ultimately be limited by the interconnect. This is counter to everything the market expects from future semiconductor products."
In related news, AlliedSignal acquired Nanoglass LLC, the former joint venture between AlliedSignal and Nanopore Inc. Early on, TI technologists recognized that emerging dielectric technology at Nanopore, which initially targeted applications in refrigeration insulation, had a potential for its leading edge IC applications. TI was instrumental in the three-way cooperation that has culminated in AlliedSignal commercializing Nanoglass and TI successfully incorporating it into its leading edge damascene technology for 0.15-?m and beyond. - P.B.