Issue

Its good to be back where the action all begins

05/01/1998

Robert Ha avind

It`s good to be back where the action all begins

Glad to be back with you all again, after a two-year stint with Computer Design, PennWell`s magazine for design managers and senior engineers, covering the fabrication of processor-based electronic systems. It was enlightening to see the world of semiconductor manufacturing from the other side of the fence (and indeed there does appear to be quite a high fence between circuit designers and the fabrication community). Design engineers cobble together their creations - whether application-specific ICs (ASICs), programmable logic, or board designs - on powerful workstations, with design rules built into their computer-aided-design (CAD) software. They get the design rules from their captive fab, from a foundry, or from an independent library. Designers just assume that circuit dimensions will keep shrinking, and that they will be able to cram more and more circuitry, running at ever higher speeds, onto a tiny die.

How that happens is your problem. Most designers could care less about the difficulties of fabricating their circuits. In fact, more than one design group has gone ballistic after a carefully crafted and verified circuit design either did not work or failed to meet performance goals on first pass silicon. These failures occur for a number of reasons, chief among them the growing interconnect delays introduced as CDs shrink and lines are packed more densely, thus increasing RC time constants. Design software was originally devised when transistor switching delays were the main culprits, and interconnects were taken for granted.

Now, parasitic extraction and modeling of interconnects and vias is being added to the design flow to try to avoid any more such disasters. But there are other problems, too. The assumption that device models simply scale with shrinking dimensionsand lower drive voltages is becoming less and less reliable. Totally new CMOS models will be needed for tomorrow`s shallow junction devices withbarrier layers for isolation and other variants. As mixed signal devices are optimized for digital circuits, analog device designers will have to begin considering short channel effects, and steadily lower drive voltages will shrink their noise margins.

Then there is the memory bottleneck. To feed superfast, superscalar processors, more and more SRAM cache is being packed onto processor chips, and, despite conflicting processing needs, DRAM is also being added to some processors. Memory cells want high-k dielectrics to boost capacitance, while fast logic needs low k to reduce stray C. More types of trench devices are being introduced at the same time to reduce silicon real estate. These trends will offer tough challenges to process designers.

What about those design rules? In past times they could be somewhat lax, so the fab was certain it could meet the specs even with some variation in processes. Now, with tough competition over chip performance, designers want to wring every last MHz out of a process. That calls for tighter design rules, and less margin for variation. Compromises will be needed between circuit design requirements and process capabilities. Can that be factored into design software, or will some interaction be needed between circuit (and system-on-a-chip) designers and process developers? Can mask software be made more flexible, so subtle shifts in spacing and dimensions could be implemented conveniently, possibly after some experimentation on silicon? Software that enables maskmakers to apply optical proximity correction (OPC) adjustments is already moving into the market, and these programs must compensate for additional parasitics in dense circuitry introduced by OPC`s bulging corners.

In the deep submicron era, tough performance goals will probably not be reached without making intelligent trade-offs between fabrication processes and circuit layout and device structures. Maybe these capabilities can be built into software, but some interchange between the designers and those who must implement their creations might be useful as well. A quiet exchange of ideas early in the game might prevent some shouting later.