Test structure design: An opportunity for fab outsourcing
04/01/1998
Test structure design: An opportunity for fab outsourcing
Tim Turner, Keithley Instruments Inc., Cleveland, Ohio
Fabs are becoming more comfortable with collaboration in certain, isolated areas, such as the growing field of test structure design. This field has evolved to become an essential tool for process engineers. Test structures are used to measure key performance characteristics of semiconductors, in turn driving processing improvements that result in yield and product performance improvements.
In the past, as new materials and processing techniques were created, engineers developed - and closely guarded - new test structures. Yet, today, there exists a growing realization among process and design engineers that it is no longer productive to hoard their test structure expertise, and in fact their companies and the entire industry stand to gain by pooling and sharing knowledge. Several events provide evidence that this sea change in industry opinion is gaining speed:
An annual assembly sponsored by the International Conference on Microelectronic Test Structures, recently occurred in Kanazawa, Japan. The assembly is dedicated to publishing new and refined test techniques.
The trend toward standardization of test structure designs can be seen in the activities of standards organizations like JEDEC and ASTM. Both of these groups maintain growing libraries of standard test structures for various semiconductor measurements.
The Fabless Semiconductor Association (FSA) (see "FSA technology committee" on p. 46) is sponsoring programs to develop standard test chips that can be used by any of its members to evaluate the processes of participating foundries. This will prevent each company from having to perform its own qualification effort independently, thus saving both the fabs and the fabless companies time and money.
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Figure 1. As fab processes increase in complexity, more testing is required before a product is qualified. Outsourcing structure design and testing can shorten time to market.
The concept of a standardized test chip was probably first used by USC`s MOSIS program in the 1980s [1]. The MOSIS program used a common test chip to qualify and monitor various foundries that would supply wafers containing a mosaic of different small volume designs. The FSA intends to use its test chips in a similar way, but to cover the fabless industry segment, which is projected to make up as much as 6.3% of the entire semiconductor industry by 2000 [2].
The test chips contain structures for the characterization of the transistors, process control monitoring, reliability evaluations, and defect density measurements. Typical structures and tests included on the FSA chips include:
Interconnect reliability tests
Electromigration
Stress migration
Passivation integrity
Hot carrier injection tests
DC HCI
AC HCI
I/O reliability tests
Electrostatic discharge
Latchup
Junction integrity tests
Junction leakage
Gate oxide integrity
Plasma process-induced damage
Charge to breakdown
Time-dependent dielectric breakdown
Ionic contamination
Beyond foundry evaluation and monitoring, the wide use of a standardized test chip is expected to provide a benchmark for test chip designs. For example, the FSA test chip programs gather data from a wide variety of fabs and wafer processes, which should provide valuable information for improvement of tests and test structures.
Perhaps a more compelling economic benefit is shortening the time to market for new products. Over the past 10 years, the typical number of process parameters monitored by a fab has increased fivefold. All else being equal, this tends to lengthen the time it takes to qualify a product and get it to market. Outsourcing test structure design and testing can help shorten that time (Fig. 1).
A new industry is forming
A semiconductor service industry is now emerging with several new companies that offer test structure design services. In some cases, structure design is supplied by parametric test system manufacturers, such as Keithley Instruments. However, there are companies that specialize in only test structures. Such companies acknowledge that semiconductor process engineers are the only ones who can anticipate the test structure demands of new processes or special process steps unique to a fab. However, these companies do provide expertise in general test structure technology.
The market for these services has emerged over the past four years and is growing. Brenda Stoner, VP marketing at TestChip Technologies, says, "In 1994 (when TestChip entered the business), the number of companies specializing in test structure outsource services was virtually zero. A few consultants included structures with other services as a value-added proposition. Now there are at least eight companies providing test structures to IC manufacturers." Stoner expects continued market growth as foundries find themselves with resource shortages and cost reduction goals.
These problems are prompting more and more fabs to outsource a broad spectrum of test structure services. Texas Instruments is a case in point. Paul Koch, productization manager at TI`s Mixed-Signal Business Unit, explains that "Each type and style of mixed-signal device must be characterized and modeled - a very large project. Our collaboration with external specialists to outsource design of our product development, characterization, and modeling structures has improved the quality of our test die and makes more efficient use of in-house personnel." While some fabs limit outsourcing to a narrowly defined set of tasks, TI has at least one of their vendors participate in all phases of test die development, from definition and specification to test program development and actual testing.
Forces behind outsourcing
Clearly, use of outside design services and participation in test chip programs like those sponsored by FSA, require more openness by the fabs. There are four reasons why this is occurring today, when it has not flourished in the past:
Limited time for maturing technologies. Semiconductor design and process engineers are forced by the rapid advance of technology to devote their resources to only those areas that have the most value for their organizations and where they have the most expertise. It is a cost/benefit tradeoff. In many types of tests, there is a core set of measurements that has been refined and optimized to the point of mature technology. Test structures and test techniques for linewidth measurements, contact resistance, transistor characterization, and even some reliability tests have reached the point where standards exist for these measurements. These standards provide highly detailed descriptions of the design and testing of these structures to ensure accurate results in the shortest amount of time.
Crushing complexity. As semiconductor processes increase in complexity, the number of process control parameters also increases. Modern process development test chips commonly incorporate more than 10,000 individual parametric measurements. Each of these measurements must be shown to be under control in any process used for production. The structure set required to make these measurements now represents a significant collection of technology, which plays a large role in time to market and general performance of the final product. Both of these issues affect revenues.
High quality at lower cost. Outside design services lower direct and indirect engineering costs associated with test structures. The large number of details involved in the design, layout, and documentation of test structures are usually handled more efficiently by firms specializing in this technology. Specialization also ensures high quality structures that often reduce design and test iterations. For example, structures must be designed to allow application of the appropriate stress level in order to observe the desired metric. Reliable designs also require detailed engineering analysis to prevent introduction of unintentional R-L-C parasitics that destroy test integrity.
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Figure 2. Test transistor with drain enclosed by gate. This simple layout requires three pages of documentation and four different test procedures, backed by as many as 3000 lines of test code.
Better resource utilization. Companies supplying test structure designs frequently offer improved documentation (which internal resources rarely have time to complete), designs optimized for test speed and minimal silicon area, and designs with state-of-the-art resolution and accuracy (Fig. 2). In most cases, these companies have developed automated design generators or compilers that greatly increase their efficiency over manual layout techniques. Some of the companies offer complete test programs for their designs. This range of services replaces a bevy of internal designers, device engineers, process integration specialists, and layout technicians who spend many months on tasks that keep them from core mission assignments, such as process and device simulation and design of experiments.
To highlight this last point, Stoner cites the example of one company that invested ten person-years (during a ten month cycle) to develop a comprehensive test vehicle [3]. The scope of this work could probably have been completed in one to three months by a test structure service firm. Thus, outsourcing these noncore mission activities to qualified vendors is essential to fast growing fabs, and something they do in many other areas of their business.
The combination of high costs to build and maintain test structure and test technique libraries, plus the maturation of this area, has led to the current standardization trend. Each new area of semiconductor processing technology will still require new and improved test techniques. However, these now represent small incremental additions to a long list of tests and structures residing in "standard libraries" within the industry.
References
1. V. Tryee, "MOSIS Quality Assurance Plan," Final Report, 1985 Wafer Level Reliability Workshop, Technology Associates.
2. Fabless Profile Handbook, Fabless Semiconductor Association, Dallas, TX, 1997-98.
3. B. Stoner, "Outsourcing Test Structure Designs," TestChipTechnologies Inc., internal document, 1998.
Timothy Turner is director of structures engineering in Keithley`s Semiconductor Division, where he is responsible for design and development of wafer test structures and device reliability algorithms. Keithley Instruments Inc., 28775 Aurora Rd., Cleveland, OH 44139-1891; ph 216/248-0400, fax 216/248-6168.