Mask Aligners in advanced packaging
03/01/1998
Mask aligners in advanced packaging
Dietrich T?nnies, Karl S?ss KG, Munich, Germany
Michael T?pper, J?rgen Wolf, Gunter Engelmann, Herbert Reichl
Fraunhofer Institute IZM, Berlin, Germany
New packaging technologies, developed to support the increasing functionality and performance of today`s and future IC generations, increasingly use photolithography for the fabrication of high-density interconnect layers and tape automated bonding (TAB) or solder bumps. Screen printing and physical vapor deposition into a metal mask are running into resolution and reliability limits where the highest performance is needed. We have found that photolithography by proximity printing with a mask aligner meets the technological and economic demands of the industry.
Introduced in the early 1960s, mask aligners were commonly used in the IC industry until the late 1970s. Well suited to lithography with design rules >5 ?m, the simple technology of the mask aligner made it a very economical and reliable tool. But as structure sizes entered the submicron range, projection systems were increasingly employed in IC production and are now the dominant lithography tool in wafer fabs. Apart from low-volume IC production and R&D, proximity mask aligners are often used today for the production of micro-electromechanical systems such as thin film heads or airbag sensors and, since the emergence of advanced packaging technologies some years ago, have found their way back into fabs.
As the structure sizes of new chip generations shrink, yielding faster and more complex devices, intensive research on new packaging technologies is necessary to support the high performance of the bare die. Multichip modules (MCMs) combine several closely arranged bare dies mounted by flip-chip, TAB, or wire bonding on a single substrate, reducing space requirements and enhancing performance with increased communication speed between the die. Compared to conventional packaged chips mounted on a printed circuit board (PCB), MCMs provide more benefits to the automotive, telecommunication, and portable computer industries.
Chip scale packages (CSPs), about the same size as the bare die, were introduced to allow a comparably dense grouping of chips on a PCB. High performance logic chips, with their ever-increasing number of I/O pins, are especially demanding when package size has to be reduced. For example, in most cases, die are fabricated with a peripheral arrangement of the pads to allow wirebonding to the package carrier. If a part of a die is assigned for flip-chip bonding, this peripheral arrangement of the pads often leads to a very small pitch if the I/O number is high. Thus, a thin-film metallization layer for the redistribution of the peripheral contacts into a contact array with solder bumps is usually preferred.
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Figure 1. CSP with redistribution layer and solder bumps.
Lithography requirements
Various technologies are available for the patterning of MCM substrates, redistribution layers, solder, or TAB bumps. Screen printing, for example, can be used for the fabrication of MCM substrates, as well as for solder and TAB bumping. IBM`s C4 process is often performed through physical vapor deposition of bumps onto a metal mask that is aligned to the wafer. The applicability of these technologies is limited to structure sizes larger than ~100 ?m. However, the progress in IC technology has led to the development of new packaging technologies requiring a higher resolution. Therefore photolithography is increasingly used for the fabrication of high-density interconnect layers and TAB or solder bump.
On the other hand, even advanced MCM substrates, intermetallization layers, TAB, or solder bump arrays do not require a resolution better than 5 ?m. Therefore, the lithography tool used for these processes has to meet only very relaxed requirements, compared with the tools used for the fabrication of the die itself. The specific challenge for lithography in advanced packaging lies in the exposure of thick resist layers. A typical example is wafer bumping: a resist layer of 20-40 ?m thickness is patterned and used as a mould during a subsequent deposition of the bump material. The layer thickness is considerably larger than the depth of focus of common projection systems, thus leading to a loss of resolution. A similar problem arises when warped ceramic or metal substrates are used for MCMs with tolerances of several tens of microns, making it impossible to place the entire substrate surface within the focus of the projection printer.
Proximity printing
In proximity printing, the mask and substrate are separated by only a small gap (Fig. 2). The mask is illuminated by the collimated light of a high-pressure mercury lamp, exposing parts of the substrate that are not shielded by mask patterns. As this printing technique is much less sensitive to the distance between substrate and imaging optics than projection printing is, it is ideal for the patterning of thick resist and of high topography layers. The resolution of a proximity mask aligner is limited by diffraction at the mask features, which are increasingly prominent at large separation gaps. When employed in mass production, however, a modern mask aligner with optics designed to reduce these diffraction effects offers a resolution down to 2-3 ?m, keeping the gap between mask and substrate large enough to guarantee a high yield.
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Figure 2. Proximity mask aligners are especially qualified to achieve a high aspect ratio in thick resist layers. Diffraction effects are not shown, because their influence is small in typical packaging applications.
Redistribution layer
The following sections illustrate the applicability of mask aligners in advanced packaging by means of a CSP technology developed at the Technical University and the Fraunhofer Institute IZM in Berlin. During this project, all prints were performed in contact with a Karl S?ss MA6 mask aligner. In high-volume production, however, printing at a proximity gap only leads to a small loss in resolution, allowing sidewalls with a steepness of around 83? in a typical Novolak-resist.
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Figure 3. Process steps during the fabrication of a thin-film metalization for the re-routing of peripheral contact leads into a contact array on the die surface.
The fabrication of the CSP can be divided into two steps. Starting from a Si wafer containing die with peripheral pads, a redistribution layer is added to re-route the peripheral contacts into an array on the surface of the die. In the second step, the solder bumps are deposited on top of the contact array by electroplating.
Figure 3 shows the process steps during the fabrication of the redistribution layer. The photographs depict an array of contact pads for solder bumps and the surrounding rewiring. First, a plating base consisting of a 100-nm Ti:W and a 300-nm Cu layer is sputtered on the wafer. A 10-?m-thick photoresist is spun on, prebaked, and exposed using a mask aligner with a wire width of 10 ?m. After development, a 5-?m-thick Cu layer is electroplated on top of the plating base within the mould. After stripping the photoresist, the plating base is wet chemically etched to isolate the single Cu wires.
Wafer bumping
IBM`s C4 process has been commonly used for wafer bumping for many years. This technology uses a metal mask with small openings for the bump deposition. Today, however, industry is increasingly switching over to resist masks patterned by optical lithography. This technology achieves a higher yield, is less labor-intensive, and, therefore, is more economical for bump arrays with very small pitches. The resist thickness is determined by the final size of the bumps and is typically between 20 and 40 ?m. The diameters of the bump moulds cover a wide range, with structure sizes as small as 30 ?m. Figure 4 shows a bump mould patterned in a 30-?m resist layer. The mould has very steep sidewalls, an essential requirement for reliable bumping technology. Similar to the fabrication of the redistribution layer, the bumps are deposited into the resist moulds by electroplating on a sputtered plating base. After resist stripping, a tempering of the wafer induces a reflow of the solder material to yield spherical solder balls.
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Figure 4. Solder bump technology: 30 ? 30-?m moulds are patterned in a 30-?m-thick AZ4562 resist layer with a Karl S?ss MA6 mask aligner.
One of the attractive features of the wafer-bumping concept is that it allows a substantial part of the packaging to be performed on wafer-level. The current transition from 200- to 300-mm technology will lead to a reduction of packaging costs/chip and will increase the quantity of chips that can be packaged economically using wafer bumping technology.
MCMs
Like a PCB, the substrate of an MCM has to provide the interconnects between an arrangement of chips. Using co-fired ceramic or laminate substrates, simple MCMs can be fabricated with a technology similar to that used in the production of PCBs. For example, screen printing is used to form the interconnects and vias, allowing openings with diameters slightly less than 100 ?m.
High-performance modules require a very dense packaging of interconnects, however, and can no longer be produced with this technology. So-called MCM-D substrates require a technology similar to the fabrication of ICs, including patterning of the interconnect and via structures by photolithography. Many of the demands on lithography in the production of both MCM-Ds and CSPs are very similar. Even advanced modules do not require a resolution better than 5 ?m.
It is not only the achievable structure size that has a great impact on the progress of MCM technology. The electrical properties of the materials also play a key role in the overall performance of the module. The IC industry, for example, is anxious to develop dielectric materials with an ever-decreasing dielectric coefficient to improve the insulating properties of the dielectric layer. A good insulation between adjacent vias reduces crosstalk and allows an MCM design with high via density. Spin coated polyimide and benzocyclobutene (BCB)-based dielectric layers are commonly used for MCM-D substrates. Early MCM-D technologies employed wet or dry chemical etching to open the via moulds in the dielectric layers, requiring the deposition and the patterning of an etch mask prior to etching. The need to improve production efficiency led to the development of photoimageable dielectric materials. Photo-polyimides and other materials such as photo-BCB introduced a few years ago, have added promising new aspects to the fabrication of MCMs. The dielectric layer can now be patterned directly by photolithography, leading to quite obvious advantages: avoiding the coating and patterning of an etch mask reduces the number of process steps, leading to greater production efficiency. Figure 5 shows a 20-?m-thick photo-BCB layer for a high-frequency module with 20 ? 20-?m via openings patterned with a mask aligner.
Combination of MCM-C and MCM-D technology
The design of an MCM requires a close look into the compatibility of process parameters with the materials involved. For example, the production process of high-temperature co-fired ceramic (HTCC) substrates limits the choice of conductive material for the interconnects to metals that remain stable above 1000?C - frequently leading to the use of tungsten. Low-temperature co-fired ceramics (LTCC), on the other hand, permit the use of gold, silver and copper and are, therefore, better-suited to high-density interconnect modules than HTCC substrates. However, co-fired ceramics are fabricated using screen printing with an interconnect density below that of thin film substrates patterned by photolithography. As the production of co-fired ceramics is much cheaper, this process is used whenever a very high interconnect density is not required.
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Figure 5. MCM: dielectric layer with 20-?m vias in 20-?m-thick photo-BCB.
Building up the layers of an MCM usually requires an increasing density of vias and interconnects on each level. Therefore, a combination of low-cost LTCC-substrates with high-density thin film technology is proving to be an economic way to produce high-performance MCMs. A LTCC substrate provides the first interconnection levels of the MCM, completed by a high-density interconnection layer using MCM-D technology.
There are two major problems: the roughness of the surface and the unevenness of LTCC substrates. The roughness of the surface is unfavorable for the coating and patterning of thin films, thus demanding a planarization layer on top of the ceramic. For example, the above-mentioned photo-BCB has proven to be perfectly suited to covering the roughness of the substrate surface, requiring a planarization layer with a thickness of only a few microns. Planarization does not, however, help the poor flatness of the surface, which remains a big problem for photolithography. Projection printing is usually not appropriate because the substrate surface cannot be entirely placed within the focus of the system. Therefore, it is normally necessary to use proximity printing. Figure 6 depicts the thin-film wiring on top of an LTCC substrate. The large vias of the LTCC substrate are formed by screen printing and are planarized by a 15-?m-thick photo-BCB layer. The thin-film wires are connected to the LTCC substrate by vias through the planarization layer, both being patterned by proximity lithography.
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Figure 6. Combination of MCM-D technology with MCM-C.
Conclusion
New packaging technologies increasingly employ photolithographic processes to achieve the interconnect and bump density necessary for high-performance chips or MCMs. Proximity mask aligners are favored photolithographic process tools because they are especially suited for the patterning of thick resist layers, easily meet the resolution requirements, and have very low cost of ownership. Various packaging concepts are currently under development. New photoresist and dielectric materials are researched to improve process technology and to reduce production costs. For example, photoimageable BCB allows significant reduction in the number of process steps because it avoids the patterning of an etch mask. A combination of thick-film MCM-C and MCM-D technology can also decrease production costs of high-performance MCMs.
DIETRICH T?NNIES received his MS degree in physics in 1992 from the University of G?ttingen and his PhD in semiconductor physics in 1996 from the University of W?rzburg. In 1997 he joined the Karl S?ss headquarters in Munich as member of the product manager/marketing group, with special focus on mask aligner applications. Karl S?ss KG GmbH, Schleissheimer Strasse 90, D-85748 Garching-Hochbr?ck, Postfach 1809, D-85741 Garching, Germany; ph 49/89-320-07237, fax 49/89-320-07129.
MICHAEL T?PPER studied chemistry at the University of Karlsruhe, Germany, where he received his MS degree. He joined the Microperipherics Technology Center of the Technical University Berlin (TUB) in 1994 as a research scientist. He leads the group working on thin film for MCM-D and CSP redistribution in the MCM packaging department at the joint institues of the TUB and the Fraunhofer Institute of Reliability and Microintegration.
J?RGEN WOLF received his MS degree in electrical engineering in 1979. He joined the Microperipherics Technology Center of the Technical University Berlin in 1990. He has been responsible for new solder bumping techniques and the application of flip chip technology for MCMs. Since 1994 he has worked at the MCM Packaging Department at the joint institutes of the Fraunhofer Institute for Reliability and Microintegration and the Technical University Berlin.
GUNTER ENGELMANN received MSc and PhD degrees in physics from the Technische Universit?t M?nchen. From 1980 to 1987, he worked in surface science at the Max-Planck-Institut f?r Plasmaphysik in Garching near Munich. In 1987, he joined the Technische Universit?t Berlin. Since then, he has published a series of articles on bumping, UV depth lithography, and microfabrication.
HERBERT REICHL is the director of the Microperipherics Technology Center at the Technical University of Berlin (TUB) and of the Fraunhofer Institute IZM Berlin. He received his MS and PhD degrees in electrical engineering from the Technical University of Munich, Germany. Since 1987, he has been a professor at the TUB and director of the Microperipheric Center. In 1993, he became the head of the newly established IZM.