Sia Update
03/01/1998
This is the third and final installment of Solid State Technology`s review of the Semiconductor Industry Association`s (SIA) 1997 National Technology Roadmap for Semiconductors (NTRS). Chief Technical Editor Katherine Derbyshire authors the first article on front-end processes. The other articles are written by the Roadmap`s working group co-chairs for Design and Test, Defect Reduction, and Packaging and Assembly.
Renewed attention, funding needed for device scaling issues
Katherine Derbyshire, Chief Technical Editor
In recent years, the semiconductor industry has focused its research energy on lithography and interconnects. The fundamental transistor structures have been scaling relatively well, and no radical changes have been needed in the front end. However, according to R. Allen Bowling of Texas Instruments, co-chair for front end processes, the 1997 Roadmap foresees a point where the gate dielectric will no longer scale. The next several years will require much more attention and research funding for fundamental device scaling issues.
For the short term, the most difficult challenges appear to be gate dielectric scaling, channel engineering, junction scaling, and cost of ownership for large wafers. Dielectric scaling is important because thinner dielectrics allow more leakage current to tunnel through. Eventually, at an oxide thickness of 15-20 ?, the layer does not contain enough atoms to control the tunneling current, and ceases to function as a dielectric. Nitrided oxide layers are being considered for thin gates, Bowling said, but even this approach won`t work beyond the 100-nm generation (2006). Further scaling will require a high-k dielectric. Materials being considered for advanced DRAM structures - (Ba, Sr)TiO3 (BST), TiO2, and Ta2O5 - will also be gate dielectric candidates. Though they are unlikely to gain immediate acceptance, Gary Bronner, IBM`s 1-GBit DRAM process integration manager, points out that experience with DRAMs will make high-k materials easier to contemplate for logic. Bowling said DRAMs can tolerate more leakage current than transistors, as well. Thus, DRAM applications may allow material optimization that could then be transferred to logic.
Short-channel effects are also becoming more severe. As the channel gets shorter, the source and drain voltages compete with the gate voltage. The threshold voltage increases, and the transition between the on-and-off states becomes less sharp. Advanced devices will require engineering of the source and drain implants, and possibly new transistor structures to counter this effect. Beyond 50-nm channel lengths, Pierre Woerlee, a senior scientist at Philips Research and IEDM meeting co-chair, expects that double gates or other novel device structures will be required.
Junction scaling issues are motivating interest in rapid thermal processing, and smaller devices will only exacerbate the situation. Optimal device performance requires an abrupt transition between doped and undoped regions. Obtaining such profiles will require tight control of diffusion (and therefore thermal budget), both during the dopant activation anneal and during subsequent thermal processes. In particular, Bowling explained, the long ramp times of conventional furnace processing tend to flatten the dopant profile. He expects increased use of rapid thermal annealing. Elevated source/drain regions may be the long-term solution, but these will require substantial research.
The front-end processes working group also examined wafer requirements. While specifications are driven by shrinking device sizes, the wafer manufacturers must maintain quality over larger areas. Bowling said 300-mm wafers face moderate problems with surface metallics, particle control, oxidation, and stacking faults. Research should achieve the needed results through the 150-nm generation (2001), but the picture is unclear beyond that.
Beyond 2006, new device structures are likely. Besides the elevated source/drain already mentioned, sidewall spacers may help to control leakage, and selective silicide deposition would give more uniform contact resistance.
Overall, the Roadmap says, "Due to fundamental limits such as tunneling currents, scaling bulk CMOS devices beyond 100 nm will require new materials for the gate dielectric (high-k) and gate electrode (metals), as well as new device structures, such as fully depleted SOI and elevated source/drain structures. These are critical showstoppers if not solved."
KATHERINE DERBYSHIRE is chief technical editor of Solid State Technology. She received her BS degree in materials science and engineering from the Massachusetts Institute of Technology, and her MS degree in engineering materials from the University of California, Santa Barbara. Her interests include lithography, thermal processing, and fab automation and management. Solid State Technology, 10 Tara Blvd., Fifth Floor, Nashua, NH 03062.