reducing defects to manage Yield
03/01/1998
Reducing defects to manage yield
Charlie Gross, Digital Semiconductor Hudson, Massachusetts David Jensen, Advanced Micro Devices, Austin, Texas
In the 1997 edition of the SIA National Technology Roadmap for Semiconductors (NTRS), the Defect Reduction program in the Cross-Cut Technology Working Group brought an overall yield management focus to the tables. The defect reduction subjects discussed in the new roadmap included defect detection and classification hardware and software, yield modeling, electrical fault detection and isolation, and material purity requirements. In the 1994 edition, defect reduction technology was considered in terms of contamination control and was given space in the materials and bulk processing and factory integration sections.
Defect reduction is really work that results in yield and reliability improvement. A fab`s ability to acquire yield early and often is a prime success factor throughout the industry, and the technology required to do this employs critical skills that stand apart from other fab engineering disciplines.
The 1997 Roadmap defect reduction section lists five difficult challenges that are key to the semiconductor industry`s "near term" (through 2006) success:
1. Defect budget modeling. We can calculate yield targets for future generations if we tag areas of the process with maximum allowable defect targets. Developing and validating models to do this accurately is a formidable challenge. If we allocate the defect budgets incorrectly, process tool manufacturers and process developers may put their emphasis in the wrong place and miss the yield targets. If the targets are too stringent, we may be asking tool and process developers to do the impossible. SEMATECH has developed and validated a 0.25-?m defect model, but without strong support from the industry, accurate sub-0.25-?m models may come too late.
2. Via inspections. Currently, no inspection tool can see into the bottom of deep, narrow vias or trenches. During via and trench etches, defects hide on the sidewalls and bottoms of these features. The future will bring designs that require billions of vias. Process drifts that cause via defects to migrate upward must be caught in-line quickly. New tools and techniques must see into these nano-pits.
3. Trace impurities within critical process materials. Future film thicknesses will be measured in terms of single-digit atomic layers. Trace impurities in process materials can compromise these structures. Fundamental understanding of specific contaminants and their impact on product is necessary to determine what level of which impurities can do most damage.
4. Fault isolation. Picture 200 million transistors on one chip and 500 process steps, any of which could have spawned a killer defect. Our ability to determine the location of the defect that caused some generic "basic functional" test to fail, and the ability to identify the process step that caused the problem, will have to increase manyfold in the next few years. The more complex circuits become, the more difficult it will be to isolate functional or reliability faults on silicon.
5. Smart/Clean process tools. To meet 100-nm technology and high yield demands, process tools will be designed to prevent particulate formation and the tools themselves will be capable of detecting changes within their chambers that can lead to particulate formation. The tools will then self-correct or alert the operator to a potential problem. Tool suppliers will learn to model defect formation mechanisms more accurately and will supply sensors, built into the tools, that detect the onset of defect formation.
Two areas of the 1997 Defect Reduction Roadmap requirements are less stringent. Predicted device yields at probe was the foremost area for relaxation. The 1994 version of the roadmap predicted 90% yields in the first year of manufacturing for the largest possible device at a given technology node. In the 1997 Roadmap, we back off from this lofty ideal to base our defect budgets on first year manufacturing yields of 60% on large complex devices. Eighty percent yields are presumed achievable in the third year of manufacturing. This relaxation changes the defect density requirements dramatically (Table 1). On average, the resultant defect density targets are increased approximately fivefold. The new yield predictions are more realistic and achievable.
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In the surface prep section in-front end processes, we are relaxing the level of impurities in chemicals used for pre-diffusion cleans by approximately one order of magnitude (Table 2). Based on impurity levels and results seen in state-of-the-art fabs today, we believe the 1997 Roadmap more accurately reflects the necessary rate of improvement.
In summary, as device and process complexities increase steadily from one technology generation to the next, achieving the yield ramp rates that make this industry profitable will become more and more difficult. Increased focus in the areas of process and inspection tool development, defect modeling and fault isolation, will all be needed to achieve these aggressive forecasts.
CHARLIE GROSS received his BS degree in physics in 1970 from Drexel University. He is currently the senior engineering manager of the Digital Semiconductor Yield Engineering Group. Digital Equipment Corp., ph 978/568-5703, fax 978/568-4681.
DAVID JENSEN received his BS degree in mechanical engineering from Arizona State University. As an AMDassignee, he holds the position of program manager for Defect Reduction Technology at SEMATECH in Austin, TX. AMD, ph 512/356-3756, fax 512/356-7640.