Assembly and Packaging Challenges
03/01/1998
Assembly & packaging challenges
Chi Shih Chang,
SEMATECH, Austin, Texas
Ronald C. Bracken,
The Semiconductor Research Corp., Research Triangle Park, North Carolina
Alex Oscilowski, SEMATECH, Austin, Texas
In the development of the 1997 edition of the NTRS, the Roadmap Coordinating Group recognized the dramatic change in the Overall Roadmap Technology Characteristics since the 1994 edition. The needs for assembly and packaging technologies are derived from these overall technology characteristics. Table 1 illustrates assembly and packaging needs for hand-held (<$1000 battery powered electronic products) and cost performance (<$3000 notebook, desktop personal computer, telecommunication) market segments.
The greatest changes at the chip level are driven by the increase in chip speed, the materials set for wafer-level interconnect, the device density, and the power dissipation. These features drive the need for greater interconnect to and from the die, improved electrical performance, different materials for packaging, more effective thermal management, and software systems to design and model everything. The package is shrinking into a minimalist version of former standards. The chip and board become a conjugate packaging system that must provide the traditional levels of electrical, mechanical, thermal, and environmental protection, in addition to increased performance.
Most of these needs for improved performance can be met with some version of the packaging solutions that were developed over the last 5-10 years. The cost of these solutions, however, has generally exceeded the targets desired by users, and additional invention and/or development will be needed. Assembly and packaging cost/pin must decrease 5%/year on average in order to keep pace with the historical improvement in silicon productivity. Simultaneously, pin counts must increase 10-20%/year on average for assembly and packaging technology to scale with improvements in silicon transistor performance (see figure).
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Technology solutions
Area array technologies. The best technology to meet the cost/performance challenges of the next 15 years is scaleable, area array technology. This technology must provide a suite of integrated solutions, including design tools/simulators, flip chip interconnect, underfill, high-density substrates, and low-cost known good die. The flip chip interconnect and the high-density substrates pose some particularly difficult scaleability challenges.
Flip chip interconnect. Current technology does not accommodate the scaling of on-chip interconnects. The most significant challenges for packaging lie in accommodating the higher wafer interconnect density with appropriate chip-to-board interconnect. The number of interconnects needed will multiply by a factor of five over the time frame of the Roadmap.
Bump-based flip chip interconnect technology provides an opportunity to meet this demand for ever-increasing pin count and performance. The bump pitch must scale from 250 ?m today to 50 ?m in 2012 (see figure). New wafer interconnect metallurgies will require underbump metallization (UBM) and bump structures that can accommodate both Al and Cu on the wafer bond pads. Research in materials and process will be necessary to scale flip chip interconnect technology to sub-150-?m geometries cost-effectively.
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High-density substrates. New substrate technologies will be required to support bump-based flip chip interconnect scaling. The board interconnect density must accommodate the increasing density of off-chip interconnect; and cost-effective substrate capability, which combines the necessary fine-line and micro-via features, remains to be developed. Improvements are needed in both line width and spacing in order to scale from 250-?m bump pitch technology (50-?m line width/spacing between pads) down to 50-?m (10-?m/11-?m line width/spacing between pads) by 2012. Micro-via capability must also scale with line width/spacing in order to provide the "via in line" structures that will be necessary to support bump pitch densification.
Future substrates must deliver improved electrical performance with reliability levels at least equivalent to packaged components. New materials with relative dielectric constants approaching 2.0 and with coefficients of thermal expansion approaching 6.0 ppm/?C will be needed for sub-150-?m pitch substrates.
Research challenges
Significant packaging invention will be needed over the next 15 years, not just the evolution of current capabilities. Flip chip assembly should achieve very high interconnect pin counts with low inductance, delivering power to the interior of the chip, and maintaining a small footprint for the chip on the substrate. Underfill technology enables chip-to-laminate assembly, providing greater affordability to the large, dense chips in development.
In addition to research on bump-based flip chips and new substrates, research must also focus on significantly improved underfill materials and processes (Table 2). Alternative interconnects may eventually be required for stress-free, compliant, chip-to-substrate attachment. The reliability limits of flip chip on organic substrates must be more fully understood, and will require comprehensive parametric knowledge of the various packaging components involved. Integrated design tools and simulators will be needed to address the chip, package, and substrate complexity that will be inherent in sub-100-?m area array technologies.
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The traditional lines of demarcation between "packaged component" and "system" have blurred with the advent of scaleable area array technologies. Assembly and packaging technology has served as the bridge between the silicon and the system for the past three decades. A concerted effort between industry, academia, and government will be required to conduct the research necessary to meet the challenges of the next 15 years.n
CHI SHIH CHANG is a SEMATECH fellow in back-end strategic technology assessment. He has worked on the Assembly and Packaging Roadmap since 1994.
RONALD C. BRACKEN received his BS degree in chemistry from Rice University, and his PhD degree in physical chemistry from Purdue University. He is director of packaging sciences at The Semiconductor Research Corp. (SRC). He is a co-chair of the Technology Working Group for Packaging responsible for updating the 1997 NTRS. SRC, PO Box 12053, Research Triangle Park, NC 27709-2053.
ALEX OSCILOWSKI received his BS degree in materials engineering from Drexel University, and his MS degree in business administration from Boston University. In 1993, he joined SEMATECH, where he is director of advanced technology responsible for assembly and packaging, strategic technology, productivity analysis, university relations, and strategic planning.