Processing and integration of copper interconnects
03/01/1998
Processing and integration of copper interconnects
Robert L. Jackson, Eliot Broadbent, Theodore Cacouris, Alain Harrus, Maximillian Biberger, Evan Patton, Tom Walsh, Novellus Systems, San Jose, California
The conversion from aluminum to copper interconnects introduces many new processes and materials into semiconductor manufacturing, including damascene process flows and electroplating unit processes. Chemical vapor deposition (CVD) for complete copper fill may return to replace electroplating in future device generations. Many integration problems involve the thin-films that function as diffusion barriers and seed/wetting layers.
The transition from aluminum to copper interconnects in semiconductor manufacturing is rapidly accelerating, as evidenced by recent press announcements from major microprocessor companies. Two primary factors drive this transition - the lower resistivity and the increased electromigration resistance that copper offers relative to aluminum.
Both of these factors address major problems faced by microprocessor manufacturers. Beyond the 0.35-?m device generation, interconnect RC (i.e., the product of the metal resistance and the dielectric capacitance) delays significantly limit microprocessor clock speed. Recent reports [1, 2, 3] show that much of this limitation can be overcome by switching from an aluminum to a copper primary conductor, without altering the dielectric.
The primary clock-speed advantage derived from the lower resistivity of copper is achieved by introducing copper at the upper interconnect levels, where conductor lengths can be of the same order as chip size. Beyond the 0.25-?m device generation, current densities in lower interconnect levels can induce electromigration failure of traditional doped-aluminum conductors. The increased electromigration resistance of copper helps overcome this limitation.
The general process flow for fabrication of copper interconnects is now reasonably well-established [4]. In the dual-damascene process (Fig. 1), via and line levels are fabricated concurrently, while in the single-damascene process, each level is fabricated separately. The dual-damascene process involves approximately 30% fewer steps than either the single-damascene process or the subtractive process currently used to fabricate aluminum interconnects [5]. As a result, dual-damascene processing should offer a significant cost advantage.
 |
Figure 1. Dual-damascene process flow for fabrication of copper interconnects. This process flow shows the via-definition step followed by the trench-definition step.
Manufacturing implementation of the damascene process flow requires several new materials and processes, plus alterations to existing processes (Fig. 2). Two changes are particularly noteworthy. In the aluminum interconnect fabrication process, metal-etch is the critical step that defines the width and spacing of the interconnect lines, while the burden of planarizing each metal level is placed on the dielectric gap-fill and CMP steps. In the copper interconnect fabrication process, a simpler dielectric etch replaces metal-etch as the critical step that defines the width and spacing of the interconnect lines, while the burden of planarization shifts to the metal deposition and CMP steps. This article examines the primary manufacturing steps involved in fabricating copper interconnects, emphasizing the changes in materials and processes required to switch from aluminum to copper. We discuss the challenges expected for each step, as well as challenges that affect integration of the entire damascene process sequence.
 |
Figure 2. Summary of the major process technology changes required in the transition from the subtractive aluminum interconnect fabrication process to the copper damascene fabrication process.
Dielectric deposition
The first step in the fabrication of each copper interconnect level is the deposition of a thin layer of silicon nitride. This layer serves as a barrier against the diffusion of copper between metal levels, and also as an etch-stop in the dielectric etch that defines the damascene vias. Because silicon nitride has a high dielectric constant, the nitride layer should be as thin as possible to avoid adding significantly to the interlevel capacitance of the complete dielectric stack. At the same time, the nitride layer must be low-stress, dense, and pinhole-free so that its diffusion barrier properties are not compromised. High-density is also critical to the nitride layer`s performance as an etch-stop. This collection of properties may be better met by a nitride deposited using high-density plasma (HDP-CVD) methods, rather than by traditional PECVD.
Deposition of the primary silicon dioxide dielectric immediately follows deposition of the nitride etch-stop in the dual-damascene process flow. The nitride and oxide layers may be deposited sequentially in the same tool. A simple, undoped oxide deposited by PECVD will find widespread application as the primary dielectric in copper interconnects, since the gap-filling properties of HDP-CVD oxides will not be required. Fluorine-doped oxides can also be used to produce a lower dielectric constant material.
In the near future, low-k dielectrics will emerge as a replacement for silicon dioxide. Although the integration of copper with low-k dielectrics is not specifically addressed in this article, any process developed for copper interconnect fabrication should be compatible with the low-k dielectric materials that may be used in future generations.
Lithography
For each device generation, interconnect line and via dimensions are less demanding than the critical dimensions (CDs) found at the silicon level. As a result, lithographic patterning of single-damascene interconnects can take full advantage of established process flows used in front-end processing.
Dual-damascene processing, however, presents a tremendous challenge to lithographers. Trench structures must be created over topography (resulting from the previous via-etch step), presenting problems for the resist coating, exposure, and development processes. Lithography problems may fundamentally limit use of the dual-damascene process beyond one or two additional device generations, particularly at the lower interconnect levels where the tightest CDs are encountered.
Via/trench etch
Via etch processes nearly identical to those required in damascene processing are already well-established. The same etch is currently used in the fabrication of tungsten plugs for both logic and memory devices. Trench-etch is a straightforward extension of the via etch process, except that much more material must be removed at the trench level.
The dual-damascene process sequence adds a new set of difficulties to the etch process. The primary problem is that trench formation has no etch-stop. Current etches for the fabrication of aluminum interconnects completely remove the primary metal or dielectric, and the process terminates on an etch-stop material (e.g., TiN). The within-wafer etch nonuniformity can thus be overcome by a modest over-etch. In the dual-damascene process, however, trenches are etched to an intermediate point part way through the dielectric layer. The within-wafer etch nonuniformity thus translates directly into within-wafer nonuniformity in the depth of the trenches.
A layered dielectric solves dual-damascene etch uniformity problems. The oxide dielectric is deposited in two separate layers - one for the line level and one for the via level - with a thin etch-stop material like silicon nitride deposited in between. Though this method provides a stop for the trench etch, it adds cost and complexity. It also increases the inter-level capacitance of the interconnect stack, which negates some of the gain in clock speed attained with lower-resistivity copper.
Challenges to the damascene etch process increase with each passing device generation. In order to maintain the lowest possible interlevel capacitance within the interconnect stack, it is desirable to shrink the width of vias and lines proportionately with the shrink in transistor gate length, while maintaining the largest practical spacing between metal levels [6]. Thus, each passing device generation has greater via aspect-ratios and an ever-increasing burden on the via etch and metal fill processes.
Copper fill
Metal fill by CVD is well known to chip manufacturers. Via fill by tungsten CVD is common in the fabrication of aluminum-based interconnects. As interconnects transition from aluminum to copper, CVD might also be the metal fill method of choice.
However, electroplating is an attractive alternative deposition method for copper that is not available for tungsten or aluminum. Electroplating is a very inexpensive process in principle, and a number of research groups have successfully used it to fill damascene structures [7]. A potential disadvantage of electroplating is that it is a two-step process. CVDfill can be completed in one step (directly on top of the diffusion-barrier), while electroplating requires deposition of a thin seed-layer prior to the plating fill step. The seed-layer provides a low-resistance conductor for the plating current that drives the process, and also facilitates film nucleation.
Although electroplating is a two-step process, calculations indicate that it offers a lower overall cost-of-ownership (COO) than full-fill CVD (Fig. 3). This calculation assumes that the required copper thickness is 1.0 ?m, which acknowledges that large-area pads must be filled along with the finer-pitch lines and vias on each metal level. The COO calculation includes factors such as the cost of the deposition equipment, fab space, labor, and consumables, but neglects factors related to device or process yield. Each cost component is computed on a per-wafer basis, with an assigned throughput of 50 wafers/hour for each process.
< Figure 3. Cost-of-ownership comparison for copper fill by CVD vs. copper fill by electroplating. The COO calculations for seed-layer deposition, as well as the full-fill copper CVD process, are based on our direct experience with CVD copper, CVD tungsten, and PVD Ti/TiN. The COO calculation for electroplating is supported by input from semiconductor manufacturers with direct process experience. Calculations clearly favor the two-step electroplating process over the one-step CVD fill process. The cost difference is mainly due to the lower capital and chemical costs of the electroplating process. Most importantly, a well-tuned electroplating process can fill high-aspect-ratio structures (Figs. 4 and 5). The results of this comparative COO calculation change dramatically if the copper thickness is reduced from the 1.0-?m value assumed in Fig. 3 because the CVD chemical cost scales directly with thickness. Based on a copper CVD precursor price of $1.00/gram, our COO model indicates that this crossover point occurs at a copper thickness on the order of 4000 ?. For applications where thinner copper may be required, such as the fill of single-damascene vias, copper CVD becomes an attractive alternative to electroplating. Figure 4. SEM cross-section of high-aspect-ratio trenches (0.28-?m wide, 5.0 aspect ratio) filled by electroplating. These trenches were plated over a tantalum barrier layer and a copper seed-layer, both deposited by PVD. Copper contamination of the wafer bevel and backside is a significant concern for manufacturing. The most effective method to eliminate this source of contamination is to ensure that the wafer bevel and backside do not come in contact with the plating solution. Combining this method with a post-plating rinse can effectively eliminate copper contamination. Since most semiconductor process engineers have little experience with electroplating, there tends to be a natural preference for more familiar copper-fill methods (i.e., CVD, or directional PVD and reflow). However, copper electroplating`s low cost creates a strong motivation for process engineers to examine it thoroughly. The process should gain acceptance. Figure 5. TEM cross-section showing high-aspect-ratio vias (0.35-?m wide, 3.4 aspect ratio) filled by electroplating. The vias were plated over a PVD tantalum barrier layer and a CVD copper seed layer. Pre-clean, barrier and seed-layer deposition The via pre-clean, barrier deposition, and seed-layer depositions will be combined on a vacuum-integrated platform to ensure that low-resistance vias are fabricated with high yield. The pre-clean removes oxides and etch residues that contaminate the metal surface at the bottom of a via; it will initially use argon-ion sputtering. A dual-frequency RF sputtering module with an HDP source is required, so that a high level of directionality can be achieved in the sputtering process at high etch rates. During pre-clean, copper ejected from the lower layer will be re-deposited onto the via sidewalls prior to deposition of a diffusion barrier, increasing the risk of line-to-line leakage. The magnitude of this problem is yet to be determined, though it is very likely that the quantity of copper re-deposited during preclean will be insufficient to degrade device performance. Otherwise, alternate via pre-clean methods will be required selectively to remove etch residue and copper oxides in the presence of copper metal. The leading diffusion-barrier process and material is PVD of tantalum. Tantalum is an attractive barrier material because of its high melting point and its immiscibility with copper [8, 9]. It is also a highly reactive metal that forms strong metal-metal bonds, much like titanium (the standard contact layer for aluminum interconnects). Tantalum should thus provide a low-resistance Ohmic contact with excellent adhesion to copper. Doping the tantalum film with a few percent of nitrogen blocks grain boundary diffusion pathways. More heavily nitrided tantalum, produced by reactive sputtering of tantalum in the presence of nitrogen, is also a highly attractive barrier material [8, 9]. One specific advantage of PVD tantalum is the excellent step coverage achieved by the tantalum sputtering process (Fig. 6). The step coverage of PVD tantalum can be further extended by ionized PVD techniques, where a significant fraction of the atoms sputtered from the target material are ionized. Ionized PVD methods greatly enhance the step coverage of the PVD Ti/TiN deposition process [10]. At some future device generation, PVD techniques will probably not provide sufficient step coverage to deposit a diffusion barrier of the required thickness at all points within a high-aspect-ratio via. CVD diffusion barriers will then be required. The leading CVD barrier material for both copper and aluminum interconnects is TiN [11]. Alternative materials for CVD barrier layers include tungsten nitride and titanium silicon nitride. In order to produce a uniform, adherent film of electroplated copper, a seed layer must be deposited over the barrier layer. The seed layer provides a low-resistance conduction path for the plating current that drives electroplating, and functions as a nucleation layer for copper film growth. Copper is the preferred seed layer because of its high conductivity, and because it is the ideal nucleation layer for growth of the electroplated copper. Figure 6. TEM cross-section showing the conformality of a tantalum layer deposited by PVD into a high-aspect-ratio trench (0.28-?m wide, 5.0 aspect ratio). The copper seed layer plays two critical roles as a carrier of plating current. On the wafer scale, the seed layer carries current from the edge of the wafer to the center, allowing the plating current source to contact the wafer only near the edge. The thickness of the seed layer must be sufficient so that the voltage drop from wafer edge to center does not reduce the electroplating within-wafer uniformity. On a highly localized scale, the seed layer carries current from the top surface into the bottom of vias and trenches. When there is insufficient seed-layer thickness at the bottom, the via or trench will prematurely close during deposition, leaving a center void. In principle, the seed-layer thickness at the bottom of a high-aspect -ratio feature can be increased by increasing the thickness of copper deposited on the field. In practice, however, excessive seed material deposited at the field level will pinch off the via or trench, again creating a center void in the film. Although PVD copper has limited step coverage in high-aspect-ratio vias and trenches, it has been successfully applied to electroplated fill. The trench structure shown in Fig. 4 was filled using a PVD tantalum barrier layer and a PVD copper seed layer. The PVD copper process for seed-layer deposition will be adequate for the first applications of copper, where the narrowest feature widths will be ~0.3 ?m. Beyond this, the PVD copper seed layer can be extended through ionized PVD methods. As with the barrier layer, however, a CVD seed layer will probably be required in future device generations. Figure 7. SEM cross-section showing the conformality of a copper layer deposited by CVD into a high-aspect-ratio trench (0.18-?m wide, 7.2 aspect ratio). Copper CVD is attractive for seed-layer deposition primarily because it is capable of nearly 100% step coverage (Fig. 7). The 3.5:1-aspect-ratio via illustrated in Fig. 5 was filled using a CVD copper seed layer with copper electroplating. The superior step-coverage of the CVD copper process requires no additional cost relative to a PVD process; chemical costs that limit full-fill applications of CVD copper are greatly reduced because precursor usage is minimal for the very thin films required in a seed-layer application. Finally, the CVD copper seed-layer process can be extended to fill narrow vias completely in a single-damascene application, which will be a significant advantage in future device generations, where even a relatively thin seed layer could pinch off a very narrow via. CMP Copper is a readily oxidized, ductile material that is ideally suited to the CMP process. These properties translate into a very high copper removal rate, but they also contribute to dishing problems [12]. Dishing is defined as excessive removal of material in large surface-area pad features relative to smaller surface-area lines and plugs. The tantalum diffusion barrier complicates copper CMP. Once the copper layer is completely polished back, the underlying tantalum layer must also be removed from the field level. The pad/slurry combination used for copper CMP does not effectively remove tantalum. Alternative pad/slurry combinations have been developed for CMP of tantalum, but the selectivity of these combinations for tantalum relative to copper has not yet been optimized. As a result, dishing is more difficult to eliminate when a tantalum barrier layer is used, because tantalum must be polished back in the presence of exposed copper damascene features. It is thus desirable to minimize the field-level thickness of the tantalum film. Titanium nitride does not have the same selectivity problem as tantalum, since pad/slurry combinations are available that can selectively remove TiN in the presence of copper. The post-CMP clean step is a critical one for copper CMP. The bevel and backside of the wafer will most likely be exposed to copper-containing solutions during the CMP step. Any copper remaining on the bevel or backside of the wafer risks contamination of other tools within the fab. As in the electroplating process, simple cleaning methods are available to remove residual copper [13], but the risks associated with copper cross-contamination demand careful monitoring of the post-CMP clean. Conclusion The basic process flow for copper damascene conductor fabrication is now well established, but significant challenges remain before copper processing becomes routine in manufacturing. Challenges include controlling the risks of copper cross-contamination within the fab, and the lack of familiarity among semiconductor process engineers with electroplating. In dual-damascene applications, additional challenges are presented by the via-etch process and the post-via-etch lithography step used to define the trenches. Several additional issues must be addressed as copper interconnects extend to the 0.13-?m device generation and beyond: extendibility of via-etch to very high aspect ratios, step coverage of the barrier and seed layers, electroplated fill of extremely narrow vias, and integration with low-k dielectrics. The clock-speed and electromigration advantages of copper provide strong motivation to resolve all these challenges. References 1. L. Gwennap, "IC makers confront RC limitations," Microprocessor Report, August 4, 1997. 2. D. Edelstein, et al., "Full copper wiring in a sub-0.25-?m CMOS ULSI technology," Processings of the International Electron Devices Meeting (IEDM), (IEEE, New York, 1997) E31-3, Dec., 1997. 3. S. Venkatesan, et al., "A high-performance 1.8 V, 0.20-}mum CMOS technology with copper metallization," Proceedings of IEDM, (IEEE New York, 1997) E31-2, Dec., 1997. 4. S. Lakshminaryanan, J, et al., "Dual-Damascene copper metallization process using chemical mechanical polishing," Proceedings of the 11th International VLSI Multilevel Interconnection Conference, pp. 49-55, June 1994 (IEEE, New York, 1994). 5. J. G. Ryan, et al., "Technology challenges for advanced interconnects," Proceedings of the Conference on Advanced Metallization and Interconnect Systems for ULSI Applications in 1997, Materials Research Society, Pittsburgh, 1998, to be published. 6. M. T. Bohr, "Interconnect scaling - the real limiter to high performance ULSI," Proceedings of the International Electron Devices Meeting (IEDM), pp. 241-244, Dec. 1995 (IEEE, New York, 1995). 7. R. J. Contolini, et al., "Copper electroplating process for sub-half-micron ULSI structures," Proceedings of the 12th International VLSI Multilevel Interconnection Conference, pp. 322-330, June 1995 (IEEE, New York, 1995). 8. K. Holloway, et al., "Tantalum as a diffusion barrier between copper and silicon: Failure mechanism and effect of nitrogen additions," J. Appl. Phys., 71, 5433-5444, 1992. 9. K.-H. Min, K.-C. Chun, K.-B. Kim, "Comparative study of tantalum and tantalum nitrides as a diffusion barrier for Cu metallization," J. Vac. Sci. Technol. B 14, 3263-3269. 10. S. Hamaguchi, S. Rossnagel, "Liner conformality in ionized magnetron sputter metal deposition processes," J. Vac. Sci. Tech. B 14, 2603-2608, 1996. 11. G. Bai, et al., "Effectiveness and reliability of metal diffusion barriers for copper interconnects," Mat. Res, Soc. Symp. Proc., Vol. 403, Materials Research Society, Pittsburgh, pp. 501-506, 1996. 12. J. M. Steigerwald, et al., "Metal dishing and oxide erosion in the chemical mechanical polishing of copper used for pattern delineation," Proceedings of the Conference on Advanced Metallization for ULSI Applications in 1994, R. Blumenthal, G. Janssen, eds., Materials Research Society, Pittsburgh, pp. 55-60, 1995. 13. V. M. Dubin, et al., "Cleaning in Cu metallization technology," Proc. of the Conf. on Advanced Metallization and Interconnect Systems for ULSI Applications in 1997, Materials Research Society, Pittsburgh, 1998, to be published. For more information, contact Novellus Systems, 3970 N. First Street, San Jose, CA 95123; ph 503/685-8360, fax 503/685-8399.
