Single wafer processing of in situ-doped polycrystalline si and si1-xGex
03/01/1998
Single-wafer processing of in situ-doped polycrystalline Si and Si1-xGex
D. Bensahel, Y. Campidelli, C. Hernandez, F. Martin, I. Sagnes, France Telecom-CNET, Meylan, France
D.J. Meyer, ASM America, Phoenix, Arizona
This article demonstrates the industrial feasibility of single-wafer CVD for key advanced BiCMOS (=0.35 ?m) and CMOS (=0.18 ?m) processing steps. In situ As-doped amorphous silicon layers improve electrical performance in BiCMOS devices with a reduced number of process steps. We demonstrate reproducible stacked layers of poly-Si1-xGex/Si with Ge contents ranging from 0-100% and test the electrical behavior of this new gate material in 0.18-?m CMOS devices.
Polysilicon is widely used as a dopant source and contact to the emitter region in advanced bipolar and BiCMOS device structures. In this "polyemitter" structure, undoped polysilicon is typically deposited over the base region of the transistor. Implanted As diffuses into a narrow piece of the single-crystal base region to form the emitter. Use of in situ As-doped polysilicon can avoid the implantation step. However, in situ-doped polysilicon deposited by LPCVD suffers from poor wafer-to-wafer dopant uniformity due to dopant depletion effects. Further, when AsH3 is the dopant species, adsorbed decomposition species block the adsorption sites and "poison" the deposition rate [1, 2].
Today, polysilicon is the dominant gate electrode material in MOS devices. MOS circuits initially used metal gate electrodes made from Al, but the higher temperature tolerance of polysilicon allowed self-aligned gate structures. These structures greatly reduced the overlap between the gate region and the source-and-drain regions of the device. A gate material with an energy level near the mid-bandgap of Si would offer further improvement. Such materials as SixGe1-x and W/TiN have a decreased gate sheet resistance compared to polysilicon, and allow engineering of the gate-to-channel workfunction, fms, which influences the device threshold voltage.
Single-wafer modules are well suited for industrial epitaxial CVD, which is typically performed at high temperatures (>950?C). These modules can also perform lower-temperature processes for Si epitaxial and Si1-xGex heteroepitaxial structures [3]. This paper extends industrial single-wafer processing to polycrystalline Si1-xGex with x ranging from 0 (pure poly-Si) to 1 (pure poly-Ge). These layers can be n+ in situ doped for bipolar or BiCMOS devices or stacked with p+ in situ-doped or undoped silicon layers for advanced CMOS devices.
Equipment and basic trends
The ASM Epsilon 2000 is a single-wafer CVD system designed for epitaxial and polycrystalline Si and Si1-xGex. Loadlocks isolate the reaction chamber from the cleanroom ambient. A continuous N2 purge of the loadlocks and wafer transfer chamber prevents introduction of contaminants into the process chamber. The wafer rests on a support plate of relatively low thermal mass and is radiantly heated with quartz-halogen lamps from both above the wafer and below the susceptor. The process chamber can operate over a pressure range of ~5 torr to atmospheric pressure and over a temperature range of nominally 500-1200?C.
During epitaxial deposition, the substrate defines the crystalline structure. It must be well cleaned - free of interfacial oxide and related contaminants such as carbon - prior to the deposition. The relevant growth parameters are the deposition temperature, the working pressure, and the active gas fluxes. Polycrystalline deposition must also consider other properties, such as the degree of crystallinity (grain size). Crystallinity is a trade-off between the growth rate (related, to some extent, to the throughput of the process), which is a strong function of the deposition temperature, and the surface roughness. Surface roughness also depends on extrinsic parameters such as the state of the underlying surface, which can act as a nondesirable heterogeneous nucleation center. The loadlock of the machine, the leak rate of the reactor, the link between the previous oxide formation or oxide removal step, and the deposition step were optimized to control these effects and achieve uniform and reproducible depositions.
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Figure 1. Influence of AsH3 flow rate (sccm) and H2 flow rate (slm) on deposition rate and post-RTA resistivity. Tdep = 650?C, SiH4 = 350 sccm, RTA at 1025?C for 20 sec.
We chose an atmospheric pressure process with a hydrogen carrier gas to obtain high growth rates without excessive chamber wall coating. The deposition chemistry consisted of SiH4, GeH4, B2H6, AsH3, and H2, while HCl was used for in situ cleaning of the chamber.
This work exploited two major advantages of single-wafer processing:
1. The N2 environment in the loadlock of the system controlled the starting growth interface. The interface was of key importance during deposition of the polyemitter on the base for bipolar/BiCMOS applications.
2. Stacked structures relied on active gas switching and rapid temperature changes.
In situ As doping of poly-Si
The motivation for the deposition of in situ As-doped poly-Si and a-Si was its use as the emitter in advanced bipolar structures (=0.35 ?m). Such an emitter formation provided:
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a simpler technological process (one step instead of a sequence of deposition and implant steps);
a limit to the plugging effect resulting from the small areas to be filled by the deposit;
a higher electrically active doping level; and
improved control of the As diffusion profile near the base region after activation.
Since auto-doping was not a significant issue, we chose an atmospheric pressure process. We found that the surface roughness of this process was the same as that of a reduced pressure process (60 torr), but with an increased growth rate: 60 nm/min vs. 19 nm/min. Figure 1 presents the growth rate at 650?C as a function of AsH3 flow. The stable growth rate above 30 sccm of dopant flow indicates the saturation level of the As doping. Activation by rapid thermal annealing (RTA) at 1025?C for 20 sec confirms this observation. The H2 carrier gas flow rate of 20 slm provided the best balance between the on-wafer thickness uniformity and the growth rate. Changes in the H2 carrier flow rate had only a small influence on the final electrical activity of As after annealing. We investigated the effect of a so-called "template" layer, a saturation of the surface prior to Si deposition in order to increase the doping concentration at the interface. We observed that the sheet resistance of the polysilicon layer decreased when the template layer was included. However, electrical test results showed that, without the template layer, the amount of electrically active As was adequate for the architecture of the device. Thus, we improved the process throughput by eliminating the template layer. The table shows the on-wafer uniformity of the in situ As-doped poly-Si process.
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Figure 2. Schematic cross section of the single polysilicon quasi-self-aligned bipolar transistor.
We implemented this process in 0.35-?m BiCMOS devices on 200-mm substrates at the Centre Commun CNET-SGS-THOMSON. The design used a single poly quasi-self-aligned structure (Fig. 2). The challenge was both to prepare a reproducible starting interface prior to depositing the in situ As-doped amorphous Si and to develop a deposition scheme that would provide the right electrically active doping profile after RTA. The in situ deposition sequence completely removed the interfacial oxide and, hence, achieved full epitaxial alignment of the polyemitter. The static and dynamic characteristics of the devices were [4]:
tight distribution of the current gain throughout the entire 200-mm wafer;
lower base current noise than in a conventional poly-Si emitter technology; and
maximum frequency, fmax, of 54 GHz, and base-to-collector breakdown voltage of 3.5 V.
These results compare favorably with current bipolar technologies using implanted single or double poly-Si structures.
Poly-Si/Si1-xGex stacked layers for CMOS applications
Conventional CMOS processes use doped poly-Si for the gate. One limitation of this material is the lack of ability to change the gate-to-channel workfunction, fms. Some proposed CMOS device architectures for generations beyond 0.18 ?m use buried conduction channels, with a counterpart material for the gate [5]. The most desirable gate material would ideally provide an optimum value of fms for both nMOS and pMOS devices by having its energy level at the mid-gap of silicon (~ 0.55 eV). The mid-gap material should also be compatible with pre-existing industrial process technology (deposition, implant, etching, passivation) and provide performance benefits without an unreasonable increase in cost. Poly-Si/Si1-xGex (poly-SiGe) is promising, since fms increases with Ge concentration ([Ge]).
GRESSI has integrated poly-SiGe gates with [Ge] ranging from 0-100% in CMOS device structures. These layers are fully compatible with existing CMOS fabrication techniques. Two primary problems were encountered with poly-SiGe: the tendency of the layers to agglomerate, and the high sensitivity of Ge to oxygen with increasing [Ge]. (Most of the GeyOz by-products are volatile.)
Agglomeration of Si1-xGex was overcome by providing a thin "wetting" layer of deposited silicon (<3 nm) prior to the SiGe deposition [6-8]. The primary issues to resolve were the reproducibility of such a thin layer, and its impact on the resulting electrical properties.
Ge is difficult to deposit on oxide because of its high surface tension. The use of gaseous GeH4 and H2 also creates a competition between deposition and etching of the nuclei on the surface, and results in an incubation time prior to deposition. Further, any defect on the oxide surface will act as a heterogeneous nucleus. Growth of this nucleus overcomes the deposition of nuclei, causing undesired surface roughness. Greater film thicknesses resulted in higher surface roughness (Fig. 3), but the dependence of roughness on Ge content appears to be related to film thickness.
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Figure 3. Surface roughness as a function of layer thickness, measured by atomic force microscopy.
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Figure 4. Arrhenius plot for poly-Si and poly-Si1-xGex.
Depositing a Si cap in situ immediately after deposition of the SiGe avoids reactions between Ge and oxygen. The growth rate of SiGe at low temperatures is faster than that of Si (Fig. 4). Thus, the temperature was increased rapidly during the growth of the Si cap to increase the Si deposition rate.
To maintain an acceptable throughput despite the large difference in the growth rate of SiGe and Si, we deposited polycrystalline SiGe layers and a nearly amorphous Si cap. This procedure minimized diffusion of implanted boron during the anneal step (drive-in and RTA of the source-and-drain regions of the transistors), limited the interdiffusion of Ge into the Si cap layer, and also limited grain boundary diffusion of Si into the poly-SiGe layer.
Cross-sectional transmission electron micrographs of the poly-Ge and its Si sandwich before annealing showed that, although the Si cap deposition temperature was low, there was some initial crystallization from Ge nuclei. The control of the overall crystallinity of the structure is important both for dopant diffusion and for the interdiffusion of Ge and Si from one layer to the other. Secondary ion mass spectroscopy (SIMS) measurements prior to annealing demonstrated sharp interfaces between layers. After annealing (typically 800?C, 1 hr to simulate the global thermal budget of the post-gate formation processes), interdiffusion caused an apparent "loss" of Ge and its replacement by Si. The SIMS profiles further showed that the implanted boron reached the oxide interface.
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Figure 5. Flatband voltage shifts as functions of Ge content and thermal budget. All wafers received an 800?C, 1-hr anneal. Additional anneal times and temperatures are shown below each bar.
Adding B2H6 to the gas phase allowed in situ boron doping of the deposited films. In all of the cases (Si- and Ge-doped layers, or one doped and the other undoped), the transistors had high, electrically active dopant values.
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Figure 6. Threshold voltage as a function of Ge content and thermal budget on a pMOS transistor. All wafers received an 800?C, 1-hr anneal. Additional anneal times and temperatures are shown below each bar.
Interdiffusion of Ge and Si controls the fms value. Figure 5 presents the flatband voltage shift ( DVfb) between a p+ poly-Si gate and a p+ poly-SiGe/Si gate deduced from capacitance measurements. This figure presents both the DVfb shift with Ge content and its change with respect to the thermal budget when using a nominally 100% Ge gate.
Finally, we integrated this stacked material gate with advanced R&D 0.18-?m devices at the Centre Commun CNET-SGS-THOMSON. This process flow uses shallow trench isolation, 248-nm lithography, 4-nm thick gate oxide, and nitrided sidewall spacers. Figure 6 presents the threshold voltage results on pMOS transistors.
Conclusion
In situ As-doped polyemitter structures achieved better electrical characteristics than conventional polyemitter processing. Among these characteristics were lower base current noise, a 54 GHz fmax value, 3.5-V base-to-collector breakdown voltage, and a tight distribution of the current gain over the entire 200-mm wafer.
When using poly-Si1-xGex gates for CMOS applications, with x values from 0-1, interdiffusion of Ge and Si between the poly-SiGe layer and the Si cap dominated the workfunction, fms. Predictably, the thermal budget of the processes after gate formation controlled this interdiffusion.
Acknowledgment
The authors want to thank all of the industrial partners and CNET departments for their participation in this work, particularly for the early dissemination of unpublished results. It has been carried out within the GRESSI consortium between CEA-LETI and France Telecom-CNET. It has also been funded by the European SEA N? 20.331 "SIDOSI" project, in which SGS-THOMSON (France), Motorola (Scotland), and Philips (The Netherlands) were the industrial partners.
References
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4. S. Niel et al., "A 54GHz fmax Implanted Base 0.35-?m Single Polysilicon Bipolar Transistor," submitted to IEDM `97.
5. T. Skotnicki, "Advanced Architectures of 0.18 to 0.12 ?m CMOS Generations," ESSDERC `96 Proceedings, pp. 506-514, eds. G. Baccarani, M. Duran, Bologna Italy, Editions Frontieres, 1996.
6. T.J. King, J.R. Pfiester, J.D. Shott, J.P. McVittie, K.C. Saraswat, "A Polycrystalline Si1-xGex Gate CMOS Technology," IEDM `90, pp. 253-256.
7. H.C. Lin et al., "Effects of SiH4, GeH4, and B2H6 on the Nucleation and Deposition of Polycrystalline SiGe Films," J. Electrochem. Soc., Vol. 141, pp. 2559-2563, 1994.
8. S. Bodnar, C. Morin, J.L. Regolini, "Single-wafer Si and SiGe Processes of Advanced ULSI Technologies," Thin Solid Films, Vol. 294, pp. 11-14, 1997.
DANIEL BENSAHEL may be reached at France Telecom-CNET, branche d?veloppement, DTM/TFM, BP 98, 38243 Meylan-Cedex, France; ph 33/47-676-4140, fax 33/47-690-3443, e-mail [email protected].
DOUGLAS J. MEYER may be reached at ASM America, 3440 E. University Drive, Phoenix, AZ 85034-7200; ph 602/470-5909, fax 602/437-1403, e-mail [email protected].