Double gets Mosfet demonstrates 25-mm thick channel
03/01/1998
Double-gate MOSFETdemonstrates 25-nm thick channel
As feature sizes continue to shrink, researchers are proposing new transistor designs in order to maintain electrical properties. The double-gate MOSFET is one such approach. According to Hon-Sum Philip Wong and coworkers at IBM, in a presentation at the 1997 IEDM meeting, simulations show that double-gate MOSFETs could achieve continual improvement down to 20-30 nm channel lengths, provided that the channel thickness can be reduced to 10-25 nm and the gate oxide thickness is reduced to 2-3 nm.
Unfortunately, double-gate MOSFETs, which have a gate on either side of the channel, require unique fabrication as well. Vertical structures, such as the pillar transistor, require lithographic capability at least four times more stringent than the minimum gate length in order to control channel thickness. Previously reported planar structures, Wong said, have had degraded electrical properties because of poor alignment. Instead, the IBM re-searchers proposed a fabrication process based on ultra-thin SOI techniques.
First, they deposited successive layers of nitride, oxide, amorphous silicon, (a-Si), and oxide on the silicon substrate. Patterning the a-Si layer, a space-holder, defined the channel width (Wg):
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After deposition of a thick top nitride, the next mask defined two regions in the deposited film stack. The channel length (Lg) is the spacing between the regions. RIE etched the top nitride, top oxide, and a-Si in the patterned regions, stopping on the bottom oxide liner. The open areas on either side of the stack (which would become the source and drain regions) exposed the edges of the a-Si layer, as shown:
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Etching away the a-Si layer with KOH left an empty tunnel with dimensions of Wg ? Lg ? tSi, held together by the top nitride perpendicular to the plane of the figure. A conformal low temperature oxide lined the walls of the tunnel. The photo below, decorated with poly-Si, shows the empty tunnel structure:
Next, Wong said, the researchers cut a window through the bottom oxide to the substrate on one side of the tunnel only:
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The window allows the substrate to serve as a seed for selective epitaxial growth out of the window, through
the tunnel, and into the area on the other side:
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Growth continued until both recessed areas were completely filled with epitaxial silicon. CMP removed the excess silicon, using the top nitride as a polish stop. RIE recessed the source/drain islands, which were implanted using the top nitride as a self-aligned implant mask. After a phosphoric acid etch to remove the top and bottom nitrides, and a hydrofluoric acid etch to remove the oxide liner, a free-standing silicon bridge remained, connecting the source and drain islands:oxide and conformal deposition of poly-Si gate material produced this structure:
Patterning and self-aligned silicide deposition completed the process.
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Wong noted that this structure used a fairly large seed window for research purposes, but said epi growth through a much thinner tunnel had been accomplished. - K.D.