Topography simulation for interconnect deposition
02/01/1998
Topography simulation for interconnect deposition
Juan C. Rey, Junling Li, Victor Boksha, Technology Modeling Associates, Sunnyvale, California
D. Adalsteinsson, J.A. Sethian, Department of Mathematics, University of California, Berkeley
New process simulation programs can closely model the complex structures of ULSI interconnects. Level-set methods simulate and predict the structure of evolving surfaces in three dimensions, such as that seen in thin-film deposition. Models rely upon iterative calibration using empirical results. The ramifications of process or design changes can be predicted, and reliability-related problems such as void formation during thin film deposition can be prevented.
Interconnect electrical characteristics strongly influence deep-sub-micron IC circuit performance. Consequently, there is a strong and growing interest in modeling tools able to simulate
IC interconnect processes. Topography modeling tools are the most recent members of the TCAD (Technology Computer-Aided Design) family of simulation support tools.
Traditionally, process and device engineers in semiconductor manufacturing use TCAD simulators to specify, analyze, optimize, and design new IC processes and devices. The most commonly used tools model "front end" processes such as ion implantation, oxidation, diffusion, and polysilicon deposition and patterning. These tools can simulate the electrical characteristics of active devices.
However, topography simulators are becoming more important in the "back-end" portion of the process flow. They are needed to model the complex deposition, etch, spin-on glass, CMP, and reflow processes used to build the interconnect layers. The two- and three-dimensional structures created with the topography simulator can then be used to analyze the electrical characteristics of the interconnects (e.g., to extract parasitic capacitance and resistance).
While front-end TCAD simulation is a well-established technology with more than 20 years of industry and university R&D, development of back-end TCAD simulators did not begin until the mid-1980s. This late start, combined with the complexity and variety of the chemical and deposition processes used in microelectronics manufacturing, delayed the rapid spread of this type of simulation tool.
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Several research institutions pioneered the development of key back-end models, including Stanford University`s SPEEDIE (Stanford Process Emulator for Etch and Deposition in IC Engineering) [1] and the University of Arizona`s etch and deposition program EVOLVE [2]. These programs primarily model chemical and physical mechanisms.
It was not until early in this decade that commercial tools incorporated the models developed in academic environments. Commercial topography simulators like Terrain [3], a topography modeling tool from Technology Modeling Associates, can currently model full three-dimensional structures. These new models can delineate trade-offs between different process alternatives in a complete process flow, and they can be calibrated for many unit processes to analyze topography characteristics with different layout changes.
Engineering requirements
Engineers involved with the development of back-end IC interconnect processes face many challenges, ranging from difficult integration issues to detailed process tuning. Their diverse engineering challenges can be characterized broadly as unit-process development and process-integration needs.
A unit-process development engineer usually works on either a single process or the tight integration of two consecutive processes. The engineer is required to answer such questions as: Will a void develop when filling contact holes for the next 0.25-?m technology? How will the side wall slope created during etch change with pitch variation?
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Figure 1. Block diagram of the main functional blocks that must be incorporated in a topography process simulator.
A process-integration engineer usually looks for the best combination of processes to achieve certain characteristics in a final product. Once a generic process is established, a series of "what-if" scenarios is analyzed to optimize the process. Typical questions at this stage are: What is the impact on the final structure if the mask misalignment is 0.03-?m? What if the step coverage of the passivation layer drops by 10%?
Although both unit-process and process-integration groups interact closely and have similar modeling needs (see table), their requirements are different in several important ways. Unit-process development requires the simulation of complex layouts, and performance is a major concern. Process-integration groups usually do process tune-up with simple arrays of lines/spaces or contact holes, and physical models are critical to capture key process characteristics accurately.
These requirements can be translated into two operation modes for a simulation tool: a slow but accurate mode to fulfill process engineering needs, and a fast mode that can model a large number of process steps with simple models for process integration.
Topography modeling components
Many of the processes used in microelectronics manufacturing involve sub-atmospheric pressure regimes, and dimensions that are a few square micron in area. Under these conditions, the topographical changes at the wafer surface are strongly influenced by the fluxes of different reactants to each surface point.
For plasma-based processes, the model must consider the angular and energy distributions of ions at the wafer surface. Ions influence topographical changes by physical sputtering, or by enhancing deposition or etch characteristics. For most processes, the ion mean-free-path is on the order of the plasma sheath thickness (typically a few millimeters), and because of this, Monte Carlo techniques can conveniently model the required distributions.
In lithography and concentration-dependent etch development, the material properties of the substrate can profoundly influence the rate of surface movement. To account for these mechanisms, one must determine the substrate properties before the time-dependent topography changes can be simulated.
After the characteristics of both the reactive species and the substrate are determined, the model calculates fluxes of chemical radicals, deposition precursors, and ions at every point of the wafer surface in the simulation region. Many transport mechanisms have to be considered, including direct flux from the gas phase, re-emission, deposition of sputtered material, and surface diffusion. When the topography features are much smaller than the mean free path of the active species, molecular modeling techniques are used and mandate that fluxes be re-calculated every time the surface moves (to account for shadowing).
Fluxes calculated in the previous step are combined using empirical or semi-empirical equations to obtain deposition/etch rates at every point of the wafer surface (Fig. 1). The rates are interpreted as the speed of the surface in the direction of its normal - which corresponds to surface advancement. Usually the surface has to be moved in small time steps, and fluxes have to be re-calculated to account for the change of shadowing at different positions.
Several modeling techniques can simulate surface movement, but a recently developed technique called the Level Set method [4] offers the best robustness, accuracy, flexibility, and performance.
Level Set theory
The analysis and modeling of surface movement, due to deposition, etching, and photolithography processes, are a major challenge from a mathematical point of view. When surfaces move, they merge (generating voids), or create stable fronts, cusps, and sharp corners (e.g., during ion milling, or HDP-CVD). When these events occur, the mathematical representation of the evolving surface becomes critical, since the surface is often not differentiable. This lack of differentiability can create serious problems for typical algorithms.
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Figure 2. Simplified mask layout of a stacked-capacitor cell for a 64-Mbit DRAM.
Level Set methods, introduced by Osher and Sethian [5], provide an accurate and robust solution to the surface propagation problem. The method consists of defining a new function (fi) such that the surface position at every instant in time is implicitly defined as a particular level set of this new function (for convenience, the level zero is usually selected).
More precisely, the idea is to represent the evolving surface position as the set of all points (x, y, z) such that fi (x, y, z, t) = 0, where t represents the time. A convenient initial value for this level set function (fi) is given by the signed distance (d) of every point (x, y, z) in space to the initial interface, that is, fi (x, y, z, t = 0) = (?)d.
Assuming the surface is moving with a speed (F) defined along the surface normal, an equation for the level set function is then derived:
[d(fi)/dt] +F ? |grad(fi)| = 0
The position of the surface is found at every instant in time by finding the zero level set of the function (fi). One of the key advantages of this formulation is that conventional discretization techniques such as finite difference schemes can be used to solve it.
A special discretization technique called "narrow banding" [6] is commonly used to accelerate performance. The narrow banding technique consists of discretizing the complete simulation domain, but solving the level set equation only on the close neighborhood of the instantaneous surface position. The Fast Marching method [7] is a more recent surface evolution tool, applicable to cases where the speed function F is defined always positive (as in pure deposition) or negative (as during etching, or developing photoresist) and it depends only on the material properties. Under those conditions, the time at which the surface T(x, y, z) passes through the position (x, y, z) is determined by the equation:
|grad T| F = 1
This equation can be solved in a fraction of the time of any other algorithmic technique for surface movement [8]. Cases of practical importance include photoresist processing, PECVD, and the simulation of isotropic and perfectly directional etch or deposition.
Process integration of a DRAM cell
One of the most useful applications of topography simulation tools is in the area of process integration. For the complex DRAM designs created for 64- and 256-Mbit chips, it is almost impossible to visualize the three-dimensional shape of the complete structure from the layout. Many types of three-dimensional DRAM cell structures are under consideration.
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Figure 3. Simulated stacked-capacitor cell after different processes: active region and field oxide definition (top), storage node creation by patterning the second polysilicon layer (center), and patterning the third polysilicon layer (bottom).
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Figure 4. Misalignment analysis of stacked-capacitor cell second polysilicon layer: three-dimensional view (top), cut-plane through the center of the structure showing catastrophic failure due to short circuits (bottom).
Before running wafer lots to validate the manufacturability of new designs, engineers involved in process integration, layout, and drafting have to interact actively to produce three-dimensional views of the new cell. Comparing the many possible process and layout variations is greatly simplified by the use of topography simulation tools. Such visualization allows engineers to investigate layout and process variations and to minimize cell layout area.
A typical layout of a 64-Mbit DRAM stacked-capacitor cell (Fig. 2) includes three polysilicon layers and several metal layers [9]. The process sequence begins by defining the active region and the field oxide, then the storage node is created by patterning the second polysilicon layer, and finally the third polysilicon layer is patterned (Fig. 3). The process recipe up to the first metal layer patterning is used to simulate the final three-dimensional structure. An excellent match can be obtained between experimental and simulated results.
A topography modeling simulator is a powerful tool for performing "what if" analysis. A mask misalignment study is a good example (Fig. 4). In this case, the masks for the second polysilicon layer and first metal contact were intentionally misaligned. The three-dimensional and cross-sectional views show the effect of this process perturbation after a few minutes of simulation time at the cell center. The cross-sectional (two-dimensional) plot reveals catastrophic failure of the design because of the short circuit between the third and the second polysilicon layers, and between the contact and the third polysilicon layer.
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Figure 5. Calibration of the simulator is performed by matching simulation profiles with SEMs of wafer cross-sections (right).
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Figure 6. PECVD deposited oxide on an "L"-shaped metal pattern showing three-dimensional view (left), and two-dimensional cross-sectional view of the void channel (right).
Process calibration
Void formation during thin-film deposition is a critical problem affecting IC reliability. Topography tools can be calibrated to predict the position and size of voids formed, for example, during PECVD of silicon dioxide. The study of void position depending on the layout is critical to ensure that voids buried in the deposited layer are not opened in subsequent planarization steps such as CMP [10].
PECVD is modeled as a combination of a thermal CVD component and an ion-induced deposition component. The most important simulation parameters that control the profile evolution (and critical topography features such as voids) are the sticking coefficient of the thermal CVD component, the angular distribution of the reactive ions, and the ratio of the two deposition components.
Calibration of the model occurs by an iterative process. An initial correlation table is created by assuming an initial set of parameters and matching the simulation results to experimental SEM pictures. Re-running the simulation with the new correlation table creates a simulation that is somewhat closer to the empirical results, and iteration produces a very close match.
In a two-step deposition process (PECVD TEOS-based oxide followed by PECVD nitride), the model shows good correlation of step coverage with experimental results for both layers (Fig. 5). With proper calibration, it is possible to predict PECVD topography variation over very complicated patterns.
It can be difficult to develop a single PECVD process that covers both the straight middle and the "L"-shaped corners of metal lines without void formation (Fig. 6). A three-dimensional model of a typical process shows "pinched-off" voiding in the straight middle of lines, while the three-dimensional corner remains open. A two-dimensional cross-sectional model of the void channel shows that the closing point will occur at a later processing time.
Conclusion
Topography simulators are relatively new tools. They are needed to help accelerate both process integration and process development. The final structures created by a simulation tool can be used later for calculating resistance and parasitic capacitance.
In addition, the created physical models can be calibrated to predict the effect of layout and process variations before actual wafers are run. The number of experiments required when developing new technologies can thus be greatly reduced.
References
1. J. McVittie et al., SPEEDIE: A Profile Simulator for Etching and Deposition; SPIE, Vol 1392, "Advanced Techniques for IC Processing," pp. 126-137, 1990.
2. T. S. Cale, V. Mahadev, "Feature Scale Transport and Reaction During Low Pressure Deposition Processes," Thin Films; V. 22; Eds. Rossnagel S. and Ulman A.; Academic Press; p. 175, 1996.
3. TERRAIN, Topography Simulation or IC Technology; Reference Manual, Technology Modeling Associates; Sunnyvale, CA, USA.
4. J.A. Sethian, D. Adalsteinsson, "An Overview of Level Set Methods for Etching, Deposition, and Lithography Development," IEEE Transactions on Semiconductor Devices, 10-1, pp.167-184, 1997.
5. S. Osher, J.A. Sethian, "Fronts Propagating with Curvature-Dependent Speed: Algorithms based on Hamilton-Jacobi Formulations," J. Comp. Phys., 79, pp.12-49, 1988.
6. D. Adalsteinsson, J.A. Sethian, "A Fast Level Set Method for Propagating Interfaces," J. Comp. Physics, 118, pp. 269-277, 1995.
7. J.A. Sethian, "A Fast Marching Level Set Method for Monotonically Advancing Fronts," Proceedings of the National Academy of Sciences, 93, 4, 1996.
8. J.A. Sethian, "Level Set Methods; Evolving Interfaces in Geometry, Fluid Mechanics, Computer Vision and Material Sciences," Cambridge University Press, 1996.
9. W. Wakamiya, et al., "Novel Stacked-capacitor Cell for 64Mb DRAM," ICCAD, 8-5, p. 69.
10. J.G. Bornstein, et al., "3D Topography Simulation of PECVD Dielectrics over Interconnect Geometries," Proc. 3rd Int. Dielectrics for ULSI Multilevel Conference (DUMIC), pp. 411-418, 1997.
For more information, contact Juan C. Rey, Technology Modeling Associates, Inc., 595 N. Lawrence Expressway, Sunnyvale, CA 94086-3922; ph 408/328-3813, fax 408/328-0940, www.tmai.com, [email protected].