Serious trade-offs challenge process integration

02/01/1998

This is the second installment of Solid State Technology`s review of the Semiconductor Industry Association`s (SIA) 1997 National Technology Roadmap for Semiconductors (NTRS). Senior Technical Editor Ed Korczynski authors the first article here, on PIDS, but the rest are written by the Roadmap`s working group co-chairs for Interconnects, Factory Integration, and Metrology.

Serious trade-offs challenge process integration

Ed Korczynski, Senior Technical Editor, Solid State Technology

The Process Integration, Devices & Structures (PIDS) section of the 1997 NTRS deals with the big-picture tradeoffs between device design, manufacturing processes, and reliability. The main theme of this section is the need for more embedded functions in IC designs, while satisfying simultaneous challenges in interconnection and power consumption. This section includes the following major categories: memory and logic, analog and mixed signal, process flow and short flow methods, and reliability.

As this section of the NTRS deals with the inherent complexities of complete process realization, this short overview cannot begin to cover the subtleties conveyed in the NTRS itself. The following 10 "PIDS Difficult Challenges" are explained in detail in the Roadmap: integration of analog and memory with logic; reliability risk management; functional density scaling; cost-effective technology development; design for X (where X is manufacturability, reliability, etc.); signal isolation and noise reduction; atomic level fluctuations and increasing process variations; managing power, ground, signal, and clock on interconnect; function integration at low Vdd; and gate stack and source/drain (S/D) integration.

Tables within the Roadmap cover specific technology challenges within the four major PIDS categories. Distinctions are made between technology generations based on solutions that currently exist, solutions that are being pursued, and areas where no known solution exists.

For example, the DRAM cell size at the 130-nm generation (0.09 ?m2 in the year 2003) currently has no known solution. Fundamental changes will be needed in materials, cell design, and memory architecture. Short-flow technology requirements are similarly unsolved for the same generation.

Since PIDS is concerned with tradeoffs, this section of the Roadmap predicts the technologies that will be used to satisfy different end-user requirements. As the speed-power product of CMOS increases, it will replace BiCMOS and bipolar at around 180 nm (year 2000). In the long term, it is expected that low-threshold, high-gain sub-1.5 V CMOS devices will replace large-geometry, low-Vbe bipolar designs. Ultimately, full-digital CMOS chips will replace most analog designs.

Until full-digital CMOS chips are capable of replacing all analog functions, engineers will have to integrate digital and analog components for mixed-signal applications. It will be increasingly difficult to isolate noise-sensitive analog circuits from relatively noisy digital circuits as the operating frequency rises. Novel device structures may be used to enhance the signal/noise ratio, though any cost-effective solution must be compatible with the mainstream CMOS technology of the time.

Device and circuit speeds are approaching fundamental limits. Circuit elements can no longer be treated as discrete in the GHz range. The 3-cm wavelength of a 10-GHz electromagnetic signal will be close to the chip size.

Both the R&D and the manufacturing costs for new unit-processes are expected to be higher than those that are replaced. To maintain capital productivity improvements, an unprecedented systems solution may require that design, manufacturing, packaging, and test be treated as a single process.

The use of Cu and low-k dielectrics will bring about the possibility of new failure modes. Reliability test and measurement will need to change as follows: from the final IC to test structures (single device serial test to multidevice parallel test); from DC to AC (measuring failures to measuring failure predictors); and from packaged part to wafer (burn-in reliance to test, measurement and WLR).

Short-flow experiments are needed to characterize the integration of fundamentally new materials and processes in manufacturing. Standard, scaleable, and reusable test structures are needed. The greatest challenge lies is correlating short-flow experiments to full-flow manufacturing; unit-processes will have to be more fully characterized, leading to the development of fully characterized process libraries.

Process libraries may also assist in improving the ramp-rate for new fabs. Reference materials for critical metrology tools must be reproduced when processes are transferred between sites or from equipment supplier to end-user. Databases with local and reference information will greatly improve data management.