The Future of Interconnects

02/01/1998

The future of interconnects

Michael E. Thomas, National Semiconductor, Sunnyvale, California

The 1994 NTRS identified materials as key to addressing the device performance bottleneck. However, materials solutions alone will be inadequate to address needs of future VLSI de-vices. The recent NTRS empha-sizes that a much broader perspective should be taken in addressing future interconnect technology issues, involving new materials and device designs.

Recently, great strides have been made toward the transition from Al-alloy to Cu-based interconnects, driven by the higher conductivity wiring needs of VLSI circuits. It is expected that Cu wiring will begin to show up in VLSI devices by mid to late 1998. Extensive work has also been performed on new low-k dielectric constant materials, which encapsulate multilevels of wiring to reduce capacitive parasitics. These two technologies, when coupled, will provide substantial manufacturing cost reductions through process simplification and an approximate four to sixfold improvement in RC delay.

Further improvements in interconnect technology will require new architectures and designs along with new physical methods of moving multi-GHz signals at global distances (on the order of centimeters) across the device. The average interconnect length of critical global wiring has as much impact on the propagation delay as both the conductor and dielectric interconnect materials.

It is expected that the design and architecture contributions, which provide reduced global wiring lengths, could provide greater than order-of-magnitude performance enhancements. New approaches where devices and interconnects are truly intermixed in a 3-D matrix will allow greater flexibility in functionality and optimized interconnectivity.

Smart routing, systolic arrays, managed signal delays via local clock control, and on-chip/off-chip optical interconnect are a few of the options that may be implemented to enhance device performance and/or density. In the past decade, the high-device-density/low-frequency world of integrated circuits and the low-device-density/high-frequency world of RF circuits have collided.

Integrated circuit manufacturers now have to deal with VLSI RF systems, where improper wire routing and its corresponding parasitics will degrade device functionality. New design tools must be developed to handle routing problems involving billions of wiring elements (thousands of meters of interconnect on a single device). Impedance controlled wiring may also be required as functionality migrates to the integration of mixed signal/analog and digital circuit functions.

Serious technology challenges

Interconnects are perceived as one of the semiconductor manufacturing technologies with the largest potential gap between needs and capability. As the industry progresses toward the 100-nm technology node, the most difficult interconnect challenges called out in the 1997 NTRS include the following: chip reliability, process integration, barrier metal technology, dimensional control, and low-k material integration.

Because of the cost and difficulty of deviating from present interconnect approaches, different end-users will attempt to leverage existing technologies until restrictions forcing change become unbearable. Thus, microprocessor manufacturers, requiring greater performance and lower cost, have already moved toward Cu/low-k based interconnect technologies. The most advanced logic and memory technologies will, in general, be expected to use similar interconnect material and toolsets, due to cost and manufacturability considerations.

Beyond 100 nm, dimensional control and barrier materials are expected to remain key challenges; but high-aspect-ratio metal filling, FEOL benign backend processes, and identification of new interconnect systems beyond Cu/low-k are major areas of concern. Within the next decade, some of the more radical interconnect technologies involving wireless, optical, superconducting, massively parallel, or self-constructing organic or inorganic systems should begin to show feasibility.

MICHAEL THOMAS received his BSE degrees in metallurgical engineering and chemical engineering from the University of Michigan in 1973. He is co-chair of the SIA`s Interconnect Technology Working Group and is a senior member of the research staff at National Semiconductor. 2900 Semiconductor Drive, MS E-100, Santa Clara, CA95052; fax 408/721-6454, e-mail [email protected].