Next-generation metrology must meet challenges
02/01/1998
Next-generation metrology must meet challenges
Alain C. Diebold, SEMATECH Fellow, Austin, TX
Kevin Monahan, KLA-Tencor, San Jose, CA
The Metrology Roadmap section appears for the first time in the 1997 NTRS. It is one of the "crosscutting" technology areas, and thus the NTRS contains a separate metrology report and focused one-page metrology sections [1]. The metrology topics covered are microscopy, CD and overlay, film thickness and profile, materials and contamination analysis, dopant profile, in situ sensors for process control, reference materials, and correlation of physical and electrical measurements. A team of Metrology Technology Working Group (TWG) members and advisors from semiconductor manufacturers, tool suppliers, universities, and government organizations, assembled the Roadmap.
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Over the next several generations of IC technology, metrology is expected to continue to move from off-line (out of the fab) to in-line to in situ. Metrology reduces the cost of manufacturing by bringing in more robust processes, preventing scrap, and ramping and maintaining yield. In the future, MEMS should become the sensors of choice. MEMS sensors could allow self-calibration and miniaturization of measurement technology, resulting in new sensor capabilities like a mass spectrometer on a chip. Metrology tools capable of handling larger wafer sizes are needed about three to five years before their use in leading-edge pilot lines. Since volume sales of metrology tools occur as pilot lines move to volume manufacturing, metrology suppliers must wait longer for return on investment than process tool suppliers. The entire metrology infrastructure must cooperate to overcome these business challenges and provide effective tools in a timely manner.
The 10 most difficult challenges facing metrology are :
Five difficult challenges =100 nm, before 2006
Robust sensors, process controllers, and data management, allowing integration of add-on sensors
Impurity detection at levels of interest for starting materials, especially for particles, oxygen, and metallics
Measurement of the frequency-dependent dielectric constant of low k-interconnect materials at 5? to 10? base frequency
Control of processes like damascene and copper metallization
Reference materials and standard methods for gate dielectrics, thin films, and other process needs
Five difficult challenges <100 nm, before 2006
Nondestructive, manufacturing-capable microscopy for CD measurement, defect detection, and analysis
Standard electrical test methods for reliability of ultrathin silicon dioxide and new gate dielectric materials
Metrology tools for 450-mm wafers
3-D dopant profiling of transistor structures
Manufacturing-capable, physical in-line metrology that provides statistical process control for manufacture of transistors having electrical properties with ever-tightening tolerances
Table 1 shows technical requirements from the 1997 Metrology Roadmap. One of the most daunting challenges will be providing nondestructive, in-line microscopy. The current highest-resolution microscopy uses destructive methods like transmission electron microscopy, which requires time-consuming sample preparation. The faster in-line CD measurements and defect review using scanning electron microscopy (SEM) must be improved for future technology generations. Scanned probe microscopies (SPMs) such as AFM do not have the throughput of SEMs, but may be used for calibration of in-line CD SEMs. Optical and confocal optical microscopes using deep UV light are expected to provide near-term improvements for in-line optical microscopy applications. Finally, long-term research into holographic, interferometric, arrayed SEM, and arrayed SPM must begin now to meet future needs.
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Both in-line and in situ sensors are most effective when used with process tools equipped with controllers and data management systems that exchange information with the factory control system. Existing sensor technology can already improve process tool performance. Future sensors should provide more detailed information across the die, on the wafer, and eventually inside a die. The ultimate goal of sensor-based process control is to reduce process variation in real time so that the resulting film or etched structure meets tighter tolerances [2].
Key points in the other sections of the Metrology Roadmap, including the one-page discussions found in the focused Technology Roadmaps, are summarized below:
Materials characterization needs better electron and ion beam technology, surface contamination analysis for light elements, and dopant profiling capability for ultrashallow junctions. In addition, new microcalorimeter x-ray detectors have the potential to improve small-volume analysis.
Reference materials are required to develop metrology tools and to evaluate and maintain capability after installation in leading-edge production lines. Providing reference materials in the development phase of metrology tools is very difficult. Continued cooperation of the entire metrology community is necessary to ensure earlier communication of needs to organizations such as the National Institute of Standards and Technology.
Front-end processes require both physical and electrical metrology for gate stack and dopant control to enable manufacture of transistors with tighter tolerances. For example, controlling fabrication of future ultrathin dielectrics and ensuring their reliability will require extension of current optical film thickness methods to 2 nm for SiO2 and development of metrology for alternate dielectric materials. 2-D and 3-D dopant profiling remains one of the most difficult challenges for front-end processes and for process integration, devices, and structures.
New materials such as copper metallization and low k-dielectrics and new processes such as damascene (or inlaid metal) will present a challenge for interconnect metrology. Further, interconnect film thickness measurement on patterned features remains an elusive goal. High aspect ratios for contact/via and trench structures make direct observation of film thickness and defects difficult even when done in an engineering mode (nonproduction, problem-solving mode).
Lithography metrology covers both CDs and overlay measurements. Table 2 restates the CD and overlay measurement requirements from the Lithography Roadmap. In addition, the long-term microscopy development needs discussed above must have adequate funding if we are to meet the needs of lithography metrology and in-line inspection, defect review, and analysis.
Process integration, devices, and structures need measurements that enable a "statistical metrology" approach to process development. Statistical metrology is a set of procedures designed to distinguish measurement error from true process variation [3]. Some electrical test structures and physical measurement procedures allow for a more statistically significant sampling of across-the-die and across-the-wafer properties.
Summary
Off-line, in-line, and in situ metrology are all used to deliver robust processes and tools to pilot line. Due to the success of inspection technology, future fabs are expected to ramp to mature yield in a matter of months and achieve yield asymptotically to >80%. Thus, parametric performance will continue to gain in importance. Control of this performance is the fundamental purpose of metrology during semiconductor manufacturing.
References
1.Factory Integration, Front-End Processes, Interconnect, Lithography, Packaging, and Process Integration, Devices, and Structures Roadmaps.
2.These topics are covered in the Sensor-Based Metrology for Integrated Manufacturing section of the Metrology Roadmap and in the one-page contribution to The Factory Integration Roadmap.
3.C. Yu et al., "Use of Short-loop Electrical Measurements for Yield Improvement," IEEE Trans. on Semiconductor Mfg., Vol. 8, pp. 150-159, 1995.
ALAIN C. DIEBOLD is a SEMATECH Fellow and manager of Analytical Technology Infrastructure. Prior to joining SEMATECH, he worked at Allied Signal in the areas of molecular beam epitaxy and materials characterization. He is co-chair of the SIA`s Metrology Technology Working Group. SEMATECH, 2706 Montopolis Drive, Austin, TX 78741; ph 512/356-3146, fax 512/356-7640, e-mail [email protected].
KEVIN MONAHAN received his BS and PhD degrees in physics from the California Institute of Technology, and the University of California, respectively. He is co-chair of the SIA`s Metrology Technology Working Group and is director of strategic process optimization in the Metrology Group of KLA-Tencor Corp. 160 Rio Robles, H1-7100, San Jose, CA 95134; ph 408/875-5023, e-mail [email protected].