Copper wire pilot production, low-k feasability studied
02/01/1998
Copper wire in pilot production, low-k feasibility studied
At the recent IEEE Electron Device Meeting (IEDM), held in Washington, DC, chipmakers began to disclose their integration schemes for Cu metallization.
Copper offers lower resistance (1.7 ?-cm) than Al (3.0 ??-cm), dramatically reducing circuit delays. According to S.C. Sun of Taiwan Semiconductor Manufacturing Co. (TSMC), Cu metal with low-k dielectrics can achieve 16% less RC delay at the 0.13-?m generation than conventional wiring suffers at the 0.25-?m generation (see table). S. Venkatesan and coworkers at Motorola (the Motorola group) reported that in a given device generation, Cu should reduce RC delay by as much as 30%. Hierarchical wiring schemes with relaxed line pitch at the upper, current-carrying, metal layers will see even greater benefits.
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Still, according to Robert Havemann, manager of interconnect technology development at Texas Instruments, copper`s superior electromigration resistance is an even more important advantage. As wiring linewidths decrease, the current carried by those lines-which is the driving force for electromigration - increases. The Motorola group reported 10? greater electromigration lifetimes for Cu relative to Al, and D. Edelstein and co-workers at IBM (the IBM group) reported 100? greater lifetimes for Cu. The two groups used different test regimes, so their results are not directly comparable. Either value would give orders of magnitude longer lifetimes for Cu at chip-use conditions. This reliability advantage is especially important for ICs used in nontemperature-regulated environments (e.g. automotive applications).
Copper poses unique processing challenges of its own, however. First, it is extremely difficult to etch, as most Cu reaction products are nonvolatile. Cu integration is likely to require damascene processing, inlaying Cu into lines and vias etched in the dielectric (Fig. 1). Filling such high aspect-ratio features will probably require conformal deposition methods like CVD or plating. Second, Cu diffuses rapidly in Si and SiO2 and has deep level energy states in the Si band gap. Copper will diffuse into the transistors unless a suitable barrier layer is used, and will poison them once it gets there.
According to Sun, the ideal barrier layer would have low Cu diffusivity, low thickness, low resistivity, low stress, low reactivity, a smooth surface, and strong adhesion. Most researchers have used a TiN barrier layer, deposited by either PVD or CVD. According to Havemann, high aspect-ratio contact/via holes in future generations will require a CVD barrier. Sun described a MoN barrier layer deposited by MOCVD from Mo(tBuN)2(NEt2)2, reporting that Cu penetrated the barrier after annealing for 30 min at 600?C. He reported thermal stability up to 750?C with a PVD MoSiN barrier, but the resistivity increased.
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Figure 1. Motorola`s dual-inlaid Cu integration scheme; a) print vias, b) print lines, c) deposit barrier layer, and d) deposit and CMP-polish Cu.
Next, Cu can be deposited by CVD, PVD, or plating. Most researchers appear to use a PVD Cu seed layer, followed by Cu plating, but few were willing to disclose process details. Sun reported that TSMC`s integration scheme uses CVD Cu fill with a PVD wetting layer, and the Motorola group said its TiN barrier layer also served as an adhesion layer, but details were sketchy.
The IBM group appears to be closest to actually using Cu in manufacturing. Edelstein said that IBM has built fully functional microprocessor modules using the "CMOS7S" process (Fig. 2).
Meanwhile, two groups have taken the next logical step, integrating Cu with a low-k dielectric. H. Aoki and coworkers at NEC Corp. used a TiN hard mask to dry etch HSQ dielectric without the degradation commonly seen after resist ashing or chemical stripping. The TiN mask remained on the wafer during MOCVD of a TiN diffusion barrier and Cu CVD, until removed during Cu CMP. Post-CMP brush cleaning used electrolytic ionized ultra pure water, which removed particles more effectively than conventional UPW.
Eden Zielinski and coworkers at Texas Instruments integrated copper with a xerogel dielectric (Fig. 3). Xerogel, a highly porous network of SiO2, has high thermal stability and a low thermal expansion coefficient. The dielectric constant is tunable between 1.3 and 3.0, depending on porosity. The feasibility study reported at IEDM used a xerogel with 75% porosity and a dielectric constant of 1.8. According to Havemann, using xerogel in manufacturing would require optimizing the tradeoff between k and mechanical properties. Via integration will also be an issue due to moisture absorption by the xerogel.
In summary, Cu metallization is taking the first tentative steps toward use in manufacturing. Industry-leading companies are likely to begin to use it in production as early as the current 0.25-?m generation, and it will be the metal of choice by the 0.13-?m generation. Low-k dielectric integration will take longer, as it is still unclear which materials will be used.
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Figure 2. IBM`s six-level thin-wire copper structure. M1 copper (transverse) is connected by W studs to W local interconnect
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Figure 3. Texas Instruments` copper/xerogel damascene process flow.
Additional coverage of IEDM, including advances in ultrathin gate dielectrics, SOI structures, and raised junctions, will appear in next month`s issue. - K.D.