The Impact of the 300-mm transition on silicon wafer suppliers
01/01/1998
Fourth in a Series
The impact of the 300-mm transition on silicon wafer suppliers
Stephen J. Brunkhorst, David W. Sloat, MEMC Electronic Materials, St. Peters, Missouri
In the 300-mm transition, silicon wafer suppliers face challenges similar to those faced by their customers, the device makers. They must develop high-yielding, simplified processes that produce a superior product at a competitive cost; develop or procure increasingly sophisticated process equipment with a lower cost of ownership; and design factories with automated material handling systems (AMHS) and computer integrated manufacturing (CIM) to improve product quality and human productivity. In addition, wafer suppliers must satisfy the market demand for improved wafer features. This article reviews some of the issues facing silicon wafer suppliers and their customers.
Semiconductor device linewidth, which is independent of wafer diameter, drives the quality requirements of 300-mm wafers. Device makers most often cite a linewidth of 0.18 ?m as the target technology for 300-mm implementation. To accelerate the 300-mm/0.18-?m transition, the device makers also plan to demonstrate their process technology first on 200-mm wafers. In this way, 300-mm start up energies can be focused on 300-mm equipment and facilities, rather than on the new 0.18-?m process technology.
This linewidth transition means that device makers are requesting further enhancement of wafer properties. The narrower linewidths require improvements in wafer flatness, surface local light scatterers (LLS), and surface metallics. Device makers around the world agree with this direction, but consensus on specific wafer characteristics is missing in the early specification proposals. Some of the targets appear to be based on extrapolation of past requirements rather than on demonstrated or model-based process need.
The Semiconductor Industry Association (SIA) recently updated its National Technology Roadmap for Semiconductors. The draft document indicated that 0.18-?m technology will begin in 1999 on 300-mm wafers [1] (see also Roadmap coverage, p. 73).
Bulk material improvements
Current users of bulk silicon must decide whether polished wafers will be suitable for 0.18 ?m technology or whether they must move to epitaxial (epi) wafers or some other value-added product such as hydrogen or argon anneal. There is not yet a consensus on this point for DRAM production on 300 mm.
On a macro level, this is a straightforward economic decision. Epi wafers require additional wafer manufacturing steps and carry a price premium. They also provide improved performance or a yield advantage. A simplistic solution to this equation dictates that if the yield benefit is greater than the price premium, then the wafer of choice is epi.
The real-world solution is complicated by two factors. First, silicon wafer suppliers continue to improve polished wafer bulk properties by using increasingly sophisticated processes and equipment. Wafer suppliers are developing crystal with improved microdefect characteristics for advanced applications. They are controlling the crystal growth process to better manage the subtle properties such as interstitial-rich and vacancy-rich regions. Second, the device makers and wafer suppliers are defining an epi product with a reduced set of parametric requirements and a lower manufacturing cost. The properties of epi and bulk wafers are changing with time, so conclusions cannot be drawn until these development programs incubate for another year or more.
Timing of device-quality polished and epi wafers
Since most device manufacturers will first demonstrate 0.18-?m technology in 200-mm R&D facilities, the availability of device-quality 300-mm polished and epi wafers should not delay the selection of polished or epi wafers for 300-mm/0.18-?m production. Device makers will work closely with their silicon suppliers to confirm that the characteristics of the 300-mm wafers being developed meet 0.18-?m technology requirements.
The first deliveries of 300-mm-specific crystal pullers occurred in the fourth quarter of 1997, and crystal for device-quality polished wafers will be available in 1998. To pull 300-mm crystals, the wafer supplier must manage fragile quartz crucibles with polysilicon charge sizes up to 300 kg. The polysilicon meltdown cycle typically induces the maximum crucible thermal stress. The relatively recent commercial availability of granular polysilicon, manufactured by a fluidized bed process, may help address this challenge. This alternate form of raw material can be gradually added to the crucible during meltdown, providing important flexibility for large melts.
Commercial 300-mm epi reactors were delivered to the market in the second half of 1997. Early process testing of these reactors, a scale-up of 200-mm equipment, has demonstrated capabilities in line with roadmap expectations. Therefore, epi wafers will be widely available in the first half of 1998.
Crystal conversion to wafers
Slicing silicon ingots into wafers is the first major process step downstream of crystal growing. No traditional "internal diameter blade`` saws are 300-mm capable, so wire sawing is the prevalent technology for this operation (Fig. 1). At the other end of the process, double-side polishing is the most popular approach for finishing the wafer prior to final cleaning. These two "anchors" are likely to be very similar for most wafer suppliers. In between, however, there is opportunity for tremendous flexibility and innovation. The traditional process steps between sawing and polishing have included a combination of surface grinding, edge grinding, surface lapping and chemical etching. This is a fertile field for competition among the wafer suppliers for several reasons. First, double-side polishing is a powerful process that can "erase" the upstream process history. Second, further automation of wafer handling and integration of wafer tools are needed for these process steps. Third, new equipment offers improved wafer quality and process simplification.
Double-side polishing. Simultaneous front- and back-surface polishing (double-side polishing) has emerged as the process of choice. Conventional 200-mm wafer manufacture depends on an abrasive lapping process to achieve the desired wafer flatness (Fig. 2). Because the lapping step is near the midpoint of the process sequence, the downstream chemical etching and surface polishing operations require careful monitoring and control to preserve the planar properties.
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Figure 1. Wafer sawing process for 300-mm wafers.
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Figure 2. Silicon wafer manufacturing process flow
In contrast, 300-mm, double-side polishing is the final major manufacturing step. The planetary motion of the wafer between the polishing plates produces flat and parallel surfaces while improving micro-roughness. Since there are no downstream stock removal processes, flatness can be readily maintained. Site flatness of <0.25 ?m on 25 ? 25-mm sites has been demonstrated [2], and site flatness of <0.18 ?m on 25 ? 32-mm sites is anticipated as the process matures. Challenges for double-side polishing include the need for automation to improve labor productivity and optimization of process conditions to increase throughput.
After double-side polishing, wafer surfaces exhibit excellent surface finish with a typical surface micro-roughness of <10 ?. The front surface is further improved by one or more final polishing steps to obtain micro-roughness values typically <1 ?.
Polished back surface. Prior to 300 mm, the standard back surface has been finished by chemical etching. It has been the functional "handle" for wafer transport and fixturing in process tools, for both the silicon wafer maker and the device maker. Process engineers have long suspected this etched surface of particulate generation, entrapment, and shedding. The surface roughness of an etched-back wafer is three orders of magnitude greater than a polished surface, limiting laser defect inspection to a minimum detection size of 1 ?m. This limit inhibits detection of the smaller particles that can impact device performance at sub-?m linewidths.
Following double-side polishing, the back surface of a 300-mm wafer is sufficiently smooth and reflective for measurement of 0.25-?m LLSs. This capability presents both an opportunity and a challenge. The polished back surface allows the wafer maker to characterize the cleanliness of the wafer as it is delivered to the device fab. However, the wafer maker must avoid back-surface handling downstream of the double-side polisher, since the handling device could damage the surface. Any wafer transport after double-side polish must use edge handling or noncontact devices, such as a "Bernoulli`` chuck. Flatness characterization, soft laser marking, final cleaning, and surface inspection tools must all be re-engineered to avoid back-surface contact. This equipment was not available last year, but product introductions are expected in 1998.
At the device maker
Wafer back-surface LLS specifications, coupled with wafer-handling tools that do not touch the back surface, add cost and complexity to the wafer-making process. The value of this effort will be lost unless device makers also configure their lines to avoid back-surface handling. Wafer suppliers are seeking assurance from the device makers that unnecessary costs will not be designed into the wafer-manufacturing process.
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Figure 3. Deep laser mark provides maximum wafer traceability.
Wafer I.D. Wafer identification is a simple concept. Proven technology allows marking of almost any product to identify its date and source of manufacture. For silicon wafers, however, marking has historically not been universally accepted. Many device makers have expressed concern about front-surface laser marking. Deep laser mark dots, which are about 50-?m deep, would appear to be a perfect site to trap and then release particulates during wafer or, more likely, device processing. Some device makers prefer a shallow laser mark that is only 1- or 2-?m deep, but this mark is easily obscured by subsequent processing.
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Figure 4. a) Data matrix code symbol location; b) code fields, as specified in Semi standard T7-0997. All dimensions in mm unless otherwise indicated.
Some wafer suppliers would like to laser-scribe every wafer. Marking links the characteristics of each wafer to the relative position in the crystal ingot, improves traceability of process control measurements, guarantees integrity of shipping-lot identification, improves feedback from the device maker, and provides in-process identification for "lights out" factory automation.
A deep mark is ideally suited for this purpose because it can be scribed immediately after the sawing operation and before any wafer batch processing. A shallow mark must be scribed at the end of the process between polishing and final cleaning, at which point wafer position identity may already have been lost (Fig. 3).
A Semi standard (T7-0997) for laser-scribing all 300-mm wafers was approved at Semicon West 97. The standard calls for a miniature laser mark on the back surface of the wafer (Fig. 4). This mark, a two-dimensional dot matrix, can contain more data than either the Semi standard alpha-numeric or bar-code marks, as well as occupying a smaller site. It is located outside the fixed quality area (FQA), in the edge exclusion zone. The mark is readable by current commercially available recognition systems.
This back-surface mark outside the FQA is the best opportunity for full-wafer traceability in the wafer maker`s line and the device fab, without the negative issues normally associated with a deep front-surface mark. The success of this mark will depend on the willingness of device makers to evaluate it for process compatibility in pilot lines, and on the incorporation of laser-mark readers in the fab at critical points where wafer identity needs to be confirmed.
Conclusion
The transition to 300-mm-diameter wafers creates challenges and opportunities for silicon suppliers to redefine manufacturing processes and product characteristics. Some challenges, such as improvement of crystal properties, may affect the fundamental processes used by many semiconductor device makers. Other opportunities promise to reduce the cost of manufacture for the wafer supplier and establish a new competitive order. In all cases, device makers must understand the issues so that there can be a cost-effective resolution.n
References
1. "Draft," Semiconductor Industry Association, National Technology Roadmap for Semiconductors, section for Materials and Bulk Processes.
2. Randal K. Goodall, manager, "Enabling Technology Programs, I300I," presented at I300I Global Supplier Workshop, October 16, 1997.
Steve Brunkhorst is director of the 300-mm program for MEMC Electronic Materials Inc. Over the last 25 years, he has held management positions with MEMC in manufacturing, process engineering, and technology. MEMC, 501 Pearl Drive, St. Peters, MO 63376-0008; e-mail [email protected].
David Sloat is 300-mm commercial manager for MEMC. During his 10 years with the company, he has held several sales positions, most recently as sales manager for SOI products. MEMC, ph 314/279-5115, e-mail [email protected].