Industry Insights: Particle control or process control?
11/01/1999
C. Neil Berglund, Oregon Graduate Institute of Science & Technology
Who has better die yields, semiconductor companies that focus on particulate contamination or those that focus on process control and reproducibility? Since 1991, David Hodges and Robert Leachman at the University of California, Berkeley, have led a worldwide study of manufacturing practices in the semiconductor industry. One goal of the study is to characterize and understand semiconductor manufacturing best practices, and, through this understanding, to explain why some companies or fabs in different regions of the world are more successful than others. To carry out this investigation, the Berkeley group gained access to many of the major semiconductor fabs, and (under nondisclosure agreements) visited them, obtaining detailed data on all critical aspects of their manufacturing experience and practices.
A number of very important results emerged from the work, which have been detailed in various research reports, presentations, and publications.* In the course of the study, however, I noticed that there seemed to be a range of fab cultures relating to engineering yield management that could be described in terms of the relative emphasis on particulate reduction as opposed to process reproducibility and control.
Of course, fabs are concerned about both, but their degree of success in achieving high manufacturing yields showed a rather strong correlation with where they put their emphasis. Specifically, those that had the most aggressive and stringent process control as an integral feature of their engineering culture tended to have higher yields than those fabs that put their focus primarily on aggressive particulate defect reduction. The Berkeley study classified fabs at a given semiconductor design rule generation into two categories, memory and logic. The observation seemed to apply to both types for all design rule generations.
Why might this be the case? There are at least two likely reasons. The first possibility is that current yield management practices do not accurately quantify either the direct or the indirect parametric yield loss contributions caused by inadequate process control, and instead, underestimate such contributions by attributing them incorrectly to particulate defects. Engineering emphasis will be incorrectly tilted toward particulate defect reduction.
The other possibility is that better process control, and the corresponding tighter statistical distributions of measurements and data, allow more rapid and accurate identification of problems. This well-known consequence of good quality control can lead to faster and more effective learning cycles, and hence a more rapid rate of yield improvement. Better process reproducibility and control may even address unidentified or incorrectly identified parametric yield problems, resulting in both higher yields and a higher rate of yield improvement.
Parametric yield loss, the yield loss caused by processing parameters (or the resulting electrical parameters on the chip) being out of specification, is extremely difficult to model theoretically and is usually handled empirically. The models tend to focus more on yield loss due to small defects such as particulates. While many parametric yield loss mechanisms are obvious from examinations of wafer maps and detailed physical examination of the faulty chips, others are not so obvious, and many can be misinterpreted as being due to particulate defects. Furthermore, even if the mechanism is correctly identified as a parametric rather than a particulate problem, the relative contribution of such yield loss mechanisms to the overall yield loss is often difficult to extract from yield tracking and analysis measurements. As a result, the level of understanding of particulate defect yield loss in fabs is often much better than that of parametric yield loss.
The distinction between these two classes of yield loss mechanisms is important because the engineering approach to addressing them is quite different. In the case of particulate defects, the causes of particulate creation are identified and reduced relatively independent of process parametric control. In the case of engineering activities aimed at optimizing process parametric control and reproducibility, particulates play little or no role. Thus, an accurate understanding of the yield loss contributions due to each factor relative to the other is crucial to appropriate allocation of engineering effort and resources for yield improvement.
As the industry moves to feature sizes of 180nm and less on dice 22mm square and larger, one might think that ever-smaller particulate defects would have an ever-greater yield consequence relative to that of process parametric control and reproducibility. Historically, however, this has not been the case. The Berkeley study, among others, demonstrates that particulate defect yield loss has been continuously improved over time with the reduction in feature sizes. There is no reason to doubt that this trend will continue.
At the same time, there is reason to believe that process parametric control will become even more difficult. The trend to feature sizes that are smaller and smaller relative to the photolithographic wavelength used introduces new parametric sensitivities such as optical proximity effects, and makes the technologies increasingly sensitive to parametric effects such as photomask CD errors through the mask error (enhancement) factor (MEF or MEEF). Thus, it may be that strong and effective process control and reproducibility will prove even more important in the future.
Semiconductor companies that have invested in large defect-reduction programs over many years — and still find their yields are noncompetitive — should reassess both their yield management methodology and their engineering priorities. More important, if the expected increase in parametric yield loss relative to particulate defect yield loss as we move to 180nm and beyond does indeed occur, all future fabs may need to expand and modify how they manage parametric yield.
*A series of articles and reports with references to associated publications is available from the University of California, Berkeley, under the heading "Competitive Semiconductor Manufacturing Study." Information can be obtained from the U. of California web site under CSM, or by contacting the CSM Study, 3115 Etcheverry Hall, U. of California, Berkeley, CA 94720-1750, ph 510/643-1825.
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C. Neil Berglund is a professor at the Oregon Graduate Institute of Science & Technol., Dept. of Electrical & Computer Engineering, PO Box 91000, Portland, OR 97291; ph 503/748-1591, fax 503/748-1406, e-mail [email protected].