THERMAL PROCESSING: Status and future of batch, hot-wall furnaces
11/01/1999
Aubrey Helms, Jr., Robert B. Herring, Cole Porter, Alan Starner, Silicon Valley Group, Thermal Systems, Scotts Valley, California
Hot-wall batch vertical furnaces continue to provide temperature control, cost of ownership, and process variety advantages compared to single-wafer tools for wafer processing. Recent advances by vertical furnace suppliers have addressed the shortcomings of batch furnaces, including slow thermal response, long process times, and automation overhead, further improving manufacturing economics. Now, the inherent advantages of hot-wall thermal processing are being applied to a new genre of furnaces that can process small batches with short process times, addressing the needs of fabs processing large wafers and a complex mix of device production.
Today's large batch furnaces maintain an isothermal environment using well-characterized hot-wall reactor technology. Advanced temperature control techniques can ramp furnaces to process temperature with no overshoot or oscillation. Thermal uniformity across the
Such temperature control enables molecular level control of process chemistry that relates directly to precise film thickness, junction depths, dopant concentrations, and relative electrical parameters. For example, the oxidation rate of silicon is proportional to temperature and the resultant uniformity of silicon dioxide (SiO2) is proportional to thermal uniformity. Isothermal process control on today's batch furnaces can control oxides as thin as 20
This level of consistent processing across large wafer batches, which can be directly linked to yield and device parameter consistency, is a significant advantage compared to nonisothermal cold-wall technology used in single-wafer thermal processing tools. In general, single-wafer thermal processing tools do not match this wafer-to-wafer and lot-to-lot consistency.
As manufacturers begin 300mm wafer processing, the performance of hot-wall vertical batch furnaces has been successfully extended to these larger wafers. Both of the 300mm pilot fabs in operation are using vertical furnaces for many thermal processing steps. Typical 300mm load sizes have 100 product wafers. The furnace systems have integrated storage capacity for two full loads and can interface directly with automated fab material delivery systems.
Batch LPCVD reactors
When a vertical furnace is configured for low-pressure chemical vapor deposition (LPCVD), the gas flow velocity and reactant partial pressure can influence deposited film uniformity. Advanced vertical furnaces, however, have been designed using gas flow modeling to maintain laminar flow within the process chamber. This design not only ensures uniform deposition across the reaction zone, but also reduces particles deposited during processing by minimizing areas of turbulent flow that lead to gas phase reactions. In addition, dual-wall tube designs provide by-product isolation to aid in particle reduction.
Typical uniformity performance for LPCVD thin films is <5% (3-sigma) with <30, 0.20µm particles added. These specifications change slightly depending on the exact nature of the LPCVD film.
LPCVD deposition rates in a large batch furnace are low, typically 10100Å/min, which helps control film uniformity. To obtain competitive throughputs, single-wafer thermal processing tools must increase deposition rates by a factor of 10?50. This is done by increasing pressure and gas flows, but doing so leads to difficulty in controlling film uniformity and stoichiometries, and increases the probability of gas phase reactions that cause particles.
Batch furnace MTBF
Long process times and large load sizes demand high availability and high mean time between failures (MTBFs) from vertical batch furnaces. Typical uptimes are around 98% for atmospheric furnaces and 94% for LPCVD furnaces. In addition, MTBF performance is typically >1200 hrs for atmospheric furnaces and >1000 hrs for LPCVD furnaces.
By comparison, suppliers of single-wafer tools have adopted cluster platforms multiple process modules serviced by a central robot. This optimizes the throughput for the system based on process constraints. One drawback of this architecture, however, is that in current design schemes the automation subassembly is complex and responsible for most of the failures that limit overall uptime. Because of this, single-wafer tools do not perform to the high MTBF standards benchmarked by large batch furnaces.
Cost of ownership
The cost of ownership (COO) benefit of a vertical batch furnace vs. a single-wafer thermal process system comes from several parameters. First, the high MTBF and reduced scheduled maintenance of batch furnaces have a direct benefit on COO. Batch furnaces can operate for long periods before the process chamber quartz requires maintenance. Maintenance requirements are based on accumulated film thickness and vary from fab to fab, but, for example, LPCVD tubes are generally changed on a quarterly or semiannual basis. Atmospheric tubes are often only serviced annually.
In addition, the capital cost of a vertical furnace is typically lower than that of a single-wafer tool, which can be 400% more. Consider that the throughput of a single-wafer tool, which costs twice as much, is about half that of a vertical furnace.
Further, batch furnaces can produce wafer throughputs approaching 100 wafers/hr for thin oxides, a direct result of the ability to process large quantities of wafers in a single batch. Often the throughput of single-wafer systems (i.e., 50-60 wafers/hr) is constrained due to automation bottlenecks and chamber cleaning overhead time.
Shortcomings of older batch furnaces
Long process time was a shortcoming of older large batch furnaces. Typical furnace process times ranged from 4-6 hrs. High-temperature process times could approach 10 hrs. These lengthy process times were due to slow thermal response and large automation overhead. For example, typical ramp-up rates in standard vertical furnaces reach a maximum of ~10°C/min. Typical ramp-down rates are ~3°C/min. Therefore, ramp-up time between a push temperature of 700°C and process temperature of 900°C can be 20 min. In addition, extra time is required for recovery and stabilization before processing can begin.
Automation's contribution of long process times is because early versions of vertical furnaces used a single process boat that had to be unloaded and loaded after each process. At first, the use of multiple-wafer end-effectors helped reduce loading time, but this technique was vulnerable to adding particles when mechanical tolerances between the end-effector and the quartz boat could not be maintained.
Finally, with batch vertical thermal processing, we must also consider that a process abort of 150 or more wafers has the potential for causing a large financial loss. Even if the wafers can be recovered or reworked, there is still a cost penalty. Indeed, financial risk has been the driving force behind the high availability and MTBF specifications that are now typical for these systems.
Even with the success of hot-wall vertical furnaces, the continued increase in the complexity and cost of ICs is dictating that their world-class specifications must improve still more. Today, several evolving enhancements address the shortcomings of batch furnaces, including advances in heater element design, increased ramp rates, radial delta temperature control, increased batch storage, shorter automation overhead, and proactive software control.
Fast, enhanced ramp
SVG'sRapid Vertical Processor (RVP) technology was designed to address the effects of ramping and thermal response on process time [1-4]. RVP includes a patented heater element that delivers four times the power density of conventional elements enabling ramp-up rates of more than 100°C/min. This heater element consists of a stack of helical coils mapped together to form the five control zones of the furnace. Nine solid state power controllers modulate power delivered to coil groups. Each controller is capable of delivering up to 21.5kW. The temperature-ramping capability of the RVP can be separated into three distinct modes: fast ramp, enhanced ramp, and standard ramp. Because this design has reduced the thermal mass of the heater element, it results in rapid recovery and stabilization, and aids in achieving rapid ramp-down rates.
Figure 1. Wafer temperature, RDT, and maximum allowed stress for a typical oxide process using fast ramp. |
Ramp down is facilitated by forced air-cooling that recirculates air between the heater element and the quartz tube. Using a variable-speed blower, air is drawn through the furnace and directed through the annulus defined by the process tube and the heater element coils. The hot air is directed past a water-cooled heat exchanger where the air is cooled and recirculated past the heater element. Maximum ramp-down rates of 450
Although the heater element is capable of extremely high ramp-up rates, in practice, these are limited by the physical properties of silicon wafers. Silicon "slip" is generated by the temperature gradient across a wafer during a transient thermal cycle, which on a vertical furnace is measured as the radial delta temperature (RDT); RDT occurs because during ramp-up the edge of a wafer heats more rapidly than the center. The allowed RDT as a function of temperature is well known and has been calculated from the physical properties of silicon.
To accommodate the up to 100°C/min ramp rates possible with RVP while managing RDT to prevent slip, we have designed and patented a banded boat that shields the edge of the wafer in effect limiting the "thermal view" between the furnace wall and the edge of the wafer. Because this boat uses wider wafer spacing to accommodate the quartz bands, the overall load size is reduced to 50 wafers.
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The data in Fig. 1 show that the RDT stays well below the calculated slip curve (i.e., max delta T) using the RVP with a banded boat, even for ramp rates approaching 100°C/min.
(Calculations in Fig. 1 are valid only for unpatterned bare silicon wafers with a known impurity concentration. Thermal history, etching steps, chemical mechanical planarization, deposited films, etc., generally act to lower plastic deformation stress of a wafer and lead to the formation of slip at a lower RDT than predicted. Because of this, a typical rule-of-thumb is to use a 20% margin when optimizing a process.)
The end user benefits by being able to load wafers at very low furnace temperatures (~200°C) and rapidly ramp to processing temperature (~900°C). The shorter cycle time achieved by faster ramping offsets the reduced loadsize to achieve about the same throughput as a large batch process. However, the reduced time at temperature is better for advanced devices.
Figure 2. Maximum calculated center edge RDT as a function of temperature based on material and mechanical properties of prime silicon wafers. |
The RVP can still be effectively used with 150-wafer loads and average ramp-up rate between 25 and 30°C/min (i.e., "enhanced ramp"). In effect, RDT can be managed and optimized depending on the temperature range of the ramp (see table). The goal is to maximize ramp rates while maintaining RDT across a wafer well below the maximum allowable RDT curve to prevent slip (Fig. 2). The enhanced ramp mode of operation yields the highest productivity and lowest COO for a furnace. Throughput can be 70% higher than with standard ramping.
Dual-boat furnaces
The contribution of automation overhead to vertical furnace process time has been addressed by designing these systems to hold two boats within the furnace at the same time. This allows the loading and unloading of wafer batches to be transparent to furnace process time.
In the SVG system, for example, the just completed "hot boat" can be rotated to the load-unload position where it cools and is unloaded when the wafer temperature reaches a preset value. A "waiting boat" is then immediately loaded into the furnace for processing without having to wait for cool down, unload, and reload of the completed boat. With this feature, a furnace has storage capacity to hold at least two full batches of wafers, filler wafers, and test wafers. Allowing for flexibility when loading and unloading, completed batches increase the overall productivity and efficiency of a large batch furnace. In addition, this automation has proven to be very reliable.
Advanced software
Advanced vertical furnaces have also been enhanced with real-time monitoring of process parameters, which leads to real-time detection of problems that can help minimize scrap events. These parameters include analog inputs (flow rates, pressures, temperatures, and digital signals). The analog inputs and temperatures are compared to alarm and abort limits set for each process step. When a value exceeds an alarm limit, an alarm is displayed on the user interface, a buzzer, or in a light tower. Noting an alarm, the operator can correct an out-of-specification condition or abort the process if appropriate.
Additional versatility is provided for advanced vertical furnaces by customized abort subroutines. Such subroutines may be necessary when a process parameter exceeds an abort limit. They are typically written by a process engineer who specifies the appropriate response to an abort condition. Possible responses include recipe abort, recipe recovery and continuation, or system hold to await operator intervention.
Today's advanced furnaces also include software capable of statistical process control (SPC) analysis on process data after every run, generating process capability indexes (Cp and Cpk), means, standard deviations, maximums, minimums, thermal budgets, etc.
In addition to checking for values beyond the natural control limits of the system, good SPC software will look for trends that indicate the system is heading toward an out-of-control situation. A specific number of consecutive points either above or below the mean, a specific number of points rising or falling, as well as a specified allowable run-to-run change may all be defined for data analysis flagging.
If a process run is determined to be out-of-control, the system can be locked from further use and cannot be unlocked except by a privileged user. This kind of procedure gives early warning of deteriorating conditions on the system and helps prevent scrap events from occurring prior to committing product to the furnace.
Future of furnace technology
The trend in large semiconductor fabs is toward processing small quantities of a large number of different devices. The cost of the individual chips can be contained only if the fab is heavily utilized to maintain economies of scale. Thus, a logic or ASIC fab can be running hundreds of slightly different devices. Under this business model, process time is a more critical figure of merit than overall throughput or COO for process equipment. This is in contrast to large DRAM fabs where the goal is to process large quantities of the same device.
Recently, we have designed a system that adopts the benefits of the furnace to a single wafer platform [5]. It consists of a small quartz module incorporating isothermal hot-wall technology. A novel heating technique based primarily on conductive heat transfer is used to reach ramp rates approaching 100
The size of the module allows several to be stacked vertically to optimize throughput while preserving system footprint. The fully automated system consists of three stacks of modules (six modules total); a central robot can service the three stacks. The robot and control system have been chosen so that the system is not limited by the automation for process chamber residence times >60 sec.
A 30Å gate oxide has a process chamber residence time of ~120 sec and for the six-module system, a throughput of 200 wafers/hr. The throughput of the system (with two, four, and six modules) as a function of process chamber residence time is shown in Fig. 3.
Conclusion
Traditionally, the large batch furnace has been the thermal-processing workhorse within a semiconductor fab. The inherent benefits of large load size, isothermal processing, uniform film growth and deposition, high reliability, and low capital cost have ensured a large COO advantage over single-wafer thermal processing. To maintain this competitive edge, furnace technology has advanced in the areas of heater element design, increased ramp rates, RDT control, increased batch storage, shorter automation overhead, and proactive software control. Each of these improvements results in higher yield and improved economics for the end user. For tomorrow, the trend toward increased fab flexibility and shorter cycle times has resulted in the transfer of the benefits of a large batch furnace to a competitive single-wafer hot-wall furnace.
Acknowledgments
RVP is a trademark of Silicon Valley Group Inc.
References
- C. Ratliff, et al., 5th International Conference on Advanced Thermal Processing of Semiconductors-RTP'97, pp. 55?63.
- C. Porter, A. Laser, C. Ratliff, Materials Research Society Proceedings, Vol. 470, pp. 207?212, 1997.
- C. Porter, et al., SPIE Conference on Process, Equipment, and Materials Control in Integrated Circuit Manufacturing IV, pp. 42?53, 1998.
- C. Debauche, et al., European Semiconductor, Sept.1999.
- C. Ratliff, et al., 7th International Conference on Advanced Thermal Processing of Semiconductors-RTP'99, pp. 16?19.
Aubrey L. Helms, Jr. received his PhD in chemistry from Princeton University and has worked for AT&T Bell Labs, Lam Research, and Varian Associates. Helms is VP of process technology for the Thermal Systems Division of Silicon Valley Group, 440 Kings Village Rd., Scotts Valley, CA 95066-4081; ph 408/325-8890, fax 408/325-8898, e-mail [email protected].
Robert B. Herring received his BS in mechanical engineering and his MS in materials science from Rice University, and his PhD in materials science from Northwestern University. He has 25 years of semiconductor industry experience in process and equipment development. Herring is director of process technology for SVG's Thermal Systems Division.
Cole Porter has 19 years of experience in the semiconductor industry. He is a senior engineering program manager at SVG's Thermal Systems Division, currently focusing on new product technology enhancements and the 300mm program.
Alan Starner received his BS in physics from Colorado State University. He has 18 years of experience in real-time software development. Starner is software manager at SVG's Thermal Systems Division.