Technology News
11/01/1999
BACUS meets in Monterey; Intel to use phase-shift in pursuit of 130nm node
The recent 19th Annual BACUS Symposium on photomask technology and management was different from previous years. Up front, the meeting was in Monterey, CA, rather than Silicon Valley. Also, with upward of 650 attendees, it was far and away the largest such meeting, and the keynote speaker — Intel director of technology strategy Paolo Gargini — represented a photomask user, rather than a mask fabricator or equipment company.
Gargini's talk, "Driving the wavelength roadmap from 193 to 157nm," revealed some details of the ྟ lithography roadmap, which will be officially announced this month. The nominal 130nm generation will come next, either in 2001 or 2002, but after that the plan is for 3-year generational cycles. Gargini, however, commented, "I am not sure that I believe it. Intel itself plans a 2-year cycle."
The new roadmap contains some fine print. For example, the half-pitch of microprocessors in the 130nm generation will actually be 160nm, but the minimum gate widths will be 85nm. Similarly, the 100nm nominal half-pitch microprocessors will have 65nm gates and 115nm half-pitches. To achieve these gate widths, Gargini conceded that even Intel will have to use "hard" resolution enhancement techniques (RETs), including alternating-aperture phase-shifting masks. The good news for the maskmakers is that the die size will not grow beyond 22 x 22mm, implying that current 6-in. masks will be large enough.
The bad news: Gargini anticipates a one-day write time for each 130nm generation mask. "The masks dominate the cost of ownership, but the current technology is marginal or incapable of 130nm fabrication," Gargini reported.
(In a joint announcement at Semicon Taiwan, representatives from industry organizations said they would proceed with a coordinated global assessment of the economic implications of the increased R&D required to meet the technology acceleration indicated by the International Technology Roadmap for Semiconductors. These organizations included Semi; the SEAJ, Semiconductor Equipment Association of Japan; Sematech; and SEMEA, the Semiconductor Equipment and Materials European Association.
In another talk from a mask user's point of view, Masanobu Hasegawa of Canon Inc. (Utsunomiya, Japan) repeated the presentation that won the best paper award at Photomask Japan: "Practical applications of IDEAL exposure method." Even though the anticipated image contrast is only 40%, Hasegawa claimed that the two-exposure IDEAL system keeps the dreaded mask error enhancement factor (MEEF) below 2 for 140nm exposure. The required masks may be less elaborate than in other RETs.
According to Paul Warkentin, of ETEC, "All reticle materials — 11% reflective chrome, PBS resist, pellicle glue, etc. — are historical artifacts."
To meet the demands of reticle fabrication for 130nm production, maskmakers will have to employ new materials and implement new processes. Four papers discussed dry etching the chrome absorber material, which has proven to produce unexpected defect levels. Chris Constantine of Plasma-Therm Inc. described the methods employed to obtain CD uniformity in spite of the different etch characteristics of ZEP7000 resist and chrome. The plasma conditions that give the best results turned out to be opposite to expectations based on blanket etch experiments.
The MEEF, which threatens to force CD spec tightening to unimaginable levels, was another widely discussed topic. Wolf Staud of Applied Materials presented a paper authored by J. Fandrich and A. Sade of Applied Materials (Germany) that described a high-speed approach for CD uniformity mapping and monitoring. The Linewidth Bias Monitor (LBM) runs concurrently with conventional mask inspection and prepares a map showing regions where CD errors occur. A photomask previously shown to have a 23nm CD range by sampled metrology was found to have 130,000 defects localized in specific areas. The worst error found was 400nm. Many errors turned out to arise in data preparation (such things as job deck errors which caused features to be written twice), and substrate preparation, but the LBM is fast enough to monitor the mask fabrication process allowing feedback with every plate. Staud commented that today, "A 30nm range of CDs is as good as it gets, but there are still systematic errors on every plate."
With MEEF at anticipated levels for chrome-on-glass (COG) masks, 30nm CD errors will be incompatible with production of 130nm devices at acceptable yields. Much of the conference focused on RETs that might ameliorate that problem for small gates and contacts. Christopher Spence of AMD and co-authors from AMD and Mentor Graphics discussed combining optical proximity correction (OPC) and strong phase-shift for the design of poly gates. Done correctly, simulation predicts the actual resist pattern quite accurately, facilitating model-based OPC correction. However, the model-based system required 55 hours on a 5-CPU computer to correct an SRAM chip, whereas rule-based PSM/OPC required only 7.75 hours on a single processor. The high speeds resulting from narrow-gate designs are especially desirable today, according to Spence: a 400MHz chip will sell for $20, but the same device running at 650MHz will sell for $800. Privately, a knowledgeable source predicted 700MHz chips made using a similar two-exposure gate process very soon.
Gerhard Gross, litho director of International Sematech, has predicted that 100nm-node lithography will be performed with 157nm exposure, a wavelength where conventional optical glasses are opaque. Three papers described new fused silica materials with sufficient transmission and low enough thermal expansion to be used as mask substrates. The key to preparing this material is to eliminate all the OH that absorbs around 157nm without creating silicon-silicon bonds in the silica network, which also absorb. Preventing the formation of such bonds, even after extensive irradiation, requires doping with about 1% fluorine by weight. Both Lisa Moore of Corning and Hiroki Jinbo of Nikon predicted the availability of 6-in. mask plates by early 2000.
Solving other problems, such as pellicle materials and avoiding contamination by absorbing films of water (and other atmospheric species), may require more time. Purging the optical system will be 10,000 times more critical than for 193nm lithography. However, Kevin Cummings of ASML expressed confidence that all could be solved, eventually. If 157nm lithography were implemented according to current plans, it would enter production with a k1 factor of 0.4, even if lens designers push the numerical aperture as far as 0.75. Patterning a 4x mask with CDs compatible with the MEEF at such a low k1 may prove incredibly difficult. Cummings proposed choosing 6x as the nominal magnification for the 157nm systems. If the die size were reduced proportionally, so that 6" mask plates would have sufficient area, the cost of the stepper would also be reduced.
At BACUS, there are always some unexpected developments. Charles Peters of Dominion Semiconductor described a new problem of dendritic crystals growing on bright-field DUV masks, under pellicles. These 100µm contaminants contain ammonia and/or sulfur and cause up to 30% transmission loss — enough to print! While they can be removed by conventional mask cleaning, they reappear after sufficient DUV exposure unless the source of the contamination (possibly the pellicle frame) is removed. Since these defects grow even when the mask is not being used, Peters suggests that all reticles be requalified after storage. — M.D.L.
CMP being applied to 5-layer MEMS technology
An emerging, advanced five-level polysilicon surface micromachining process — four layers of structural films plus an electrical interconnect layer — pioneered at Sandia's Microelectronics Development Laboratory (MDL), Albuquerque, NM, hinges on modified chemical mechanical planarization
(CMP) processing used in IC manufacturing. Sandia's Steve Rodgers and Jeff Sniegowski have spent the past several years prototyping designs and developing the innovative process. "Our department has been working hard to baseline the technology as a reproducible manufacturing process, and we're getting there," says Rodgers. "This process should make future microelectromechanical systems (MEMS) more reliable and capable of doing increasingly complicated tasks."
 A ratcheting system fabricated with Sandia's five-level MEMS technology; 20 of these gears would fit on the period at the end of this sentence. |
Generally, the industry has been using two- and three-level polysilicon MEMS processing, successive 2-3µm layers of deposited polysilicon separated by air gaps that are initially defined by sacrificial silicon dioxide about the same thickness. Processes with tens of microns of polysilicon exist, but are typically limited to only one layer. Two levels of polysilicon provide a ground plane and one layer for MEMS structures, which is useful for fabricating simple sensors and actuators. Three levels are used to create gears with hubs. Four-level technology provides an additional layer of material that can be used to define linkage arms that move above the plane of the gears, enabling continuous 360° rotation.
The five-level technology will enable complex interacting mechanisms to be fabricated on moving platforms (see figure). The challenge with this technology is that as additional layers are added, more texture appears on the surface because the top layer acquires the characteristics of all the lower layers, including high and low spots. The result is the creation of protrusions — "mechanical parasitics" — that can interfere with operation. These parasitics can significantly constrain a MEMS; for example, if they are not taken into account, they could easily collide with teeth and prevent rotation of a gear.
To eliminate this problem, the Sandia team including process engineer Dale Hetherington modified and patented CMP to planarize the surface. "High spots are eliminated after a very thick layer of sacrificial oxide covers all previous layers. Then, with CMP, the high spots are smoothed to produce a uniform flat surface," says Hetherington.
While the five-layer process is still in the development stage and only used by Sandia's electromechanical engineering department, Rodgers expects that the process will be shared with other Sandia departments as early as next spring. "It will also be available to external commercial customers through Sandia Agile MEMS Prototyping Layout Tools Education Services program," he says.
"In the near future, this five-level polysilicon surface micromachining technology will become Sandia's standard and potentially the industry standard, replacing the more commonly used two- or three-level polysilicon surface micromachining approaches," says Rodgers. "In general, the more layers of structural material that a designer has to work with, the more complicated the device that can be fabricated. Therefore, surface micromachined components have greater functionality than bulk micromachined parts." — P.B.
ISSSDM speakers discuss interconnects, Japan, and collaboration
Three keynote speakers addressed topics ranging from interconnect technology to macroeconomic issues in Japan during the recent 1999 International Symposium on Solid State Devices and Materials, held in Tokyo.
Jim Meindl, professor at the Georgia Institute of Technology, discussed interconnect issues that will affect future device generations.
For late 1980s 1µm technology, the intrinsic switching delay of an unloaded MOSFET approached 10psec, while the response time of 1.0mm interconnects is approximately 1psec, noted Meindl. But for 0.1µm technology that will arrive early in the next decade, the intrinsic delay of a MOSFET decreases to 1.0psec while the response time of 1.0mm interconnect increases to 100psec. Thus, the latency of a 1.0mm interconnect increases from one decade faster to two decades slower than transistor delay.
Concurrent with this signal wiring dilemma, clock frequency is increasing by 100x, placing stringent new demands on the interconnects that implement the chip clock distribution network. Supply currents are increasing by 60x, while supply voltage is scaling downward by 5x, thereby imposing a huge new burden on the interconnects that implement the power distribution network. Meanwhile, maximum total wire length per chip increases by 10-20x as dimensions shrink and the number of interconnect layers rises.
The profound and pervasive nature of the interconnect problems demands commensurate response, said Meindl. Systematic exploration of interconnect limits reveals salient opportunities for addressing the interconnect problem.
Seiki Ogura, president of Halo LSI Design, Wappingers Falls, NY, spoke on the need for better collaboration. In order to reactivate the Japanese industry, he said, alliances among industries and collaboration between universities and industries are important. More activity is needed for 0.1µm mainstream technology R&D, and tax money is needed to fund these activities in Japan. Success will depend on focusing these efforts on winning technology, and will be a product of constant re-evaluation, comparing of alternative opinions, and continuous improvements by individual researchers in Japan.
Jiro Ushio, chairman of Usio Inc., a firm that provides analysis and opinion on the Japanese economy, made a number of comments on some of the broader issues affecting Japanese corporations.
Ushio noted that the tight leading environment that has weighed so heavily on the Japanese economy is at last seeing some improvement, and new stagnant demand levels have taken a turn for the better with new purchases. Japan is now ready to begin the fundamental structural reform of its economy. Against this backdrop, a range of new microbusinesses are also taking shape, spurred by the increasingly diverse needs of consumers, the rise of new financial services and information-related businesses making use of the Internet, changes in individual lifestyles, and a jump in corporate outsourcing.
Management, he added, will have to rise to some tough challenges as Japan is swept along by the forces of globalization, addressing questions concerning the competitiveness of Japan's industries and the ways in which markets will change from now on.
Bell Labs' Cochran outlines device challenges, hot topics
Device scaling, silicon-germanium, and soft errors were among the highlights of a recent address by the head of Lucent Technologies' Bell Labs VLSI Technology department. William Cochran, speaking at Chartered Semiconductor's annual Technology Forum near Boston, outlined a number of issues that are under consideration at Bell Labs to an audience of chip designers.
In addition to discussing ongoing headaches like lithography and wafer planarization, Cochran noted that historically, the industry has been able to simultaneously scale device cost, speed, density, packaging, standby current, and other factors, all in desirable directions. "That's becoming difficult," he said. "In the past we could get them all at the same time; in the future we may have to look at trading them off.
He said Bell Labs is currently evaluating designs for vertical-structure transistors, for use when traditional planar transistors cease to be practical in the 0.07- to 0.05µm design rule era (according to Bell Labs' roadmap). "The gates are cylinders instead of flat," he said. "We're looking at ways to keep the drive current from going up.
"Silicon-germanium technology is an important area of research at Bell Labs, commented Cochran. "SiGe is very integratable into systems, and the manufacturing is very integratable compared to GaAs," he said. "We're not quite as bullish on silicon-on-insulator. We're more worried about how to take care of interconnect and leakage. On the immediate horizon, we're bullish on SiGe, not SOI." One of the current internal debates at Bell Labs, he added, is "should we have regular ICs and SiGe, or just SiGe?"
Cochran noted that as device geometries have shrunk, the risk of soft errors — errors induced by radiation from metallic materials near the chip or natural sources — has grown. "We used to not be concerned about soft error rates — now we're constantly checking, even on things that have traditionally been considered static like 6T SRAM cells," he said. "You've got to make sure that dynamic circuits are fully characterized with regard to soft errors....whole new feedback loops need to be in place."
Fabrication of interconnects, he noted, costs about the same as making active components on 0.5µm devices with four metal layers. With advanced seven-layer metal devices, interconnect can account for 80% of fabrication cost. "Some of that is because innovations have decreased the cost of front-end processing, but interconnect has gotten more complex as we battle capacitance and other issues," said Cochran. "[The 80% figure] would be OK, except that we have to shift out all the equipment with each new technology node [because of the need for new materials and structures]." Intralevel capacitance and the problems of making 0.16 structures with aspect ratios over 3:1 are also issues.
The recent advent of constant reductions in power supply voltages has also become a problem, requiring redesign of analog circuits for each new process generation. Cochran noted that in the past, every chip had one power supply voltage; Lucent is trending toward a time when "virtually every device we ship will be using dual voltages."Cochran also said 300mm wafers and their promise of reduced processing costs will be needed to keep cost per gate on its traditional downward trend.
Two-layer copper for SDRAM
A 64Mbit synchronous dynamic random access memory (SDRAM) chip from Mosel Vitelic in Taiwan has been converted to a process using two levels of copper interconnect, with first-pass yield reported to be only slightly lower than the company gets with all-aluminum wiring. The project, involving 49 process steps including lithography, was completed in only 10 weeks at Applied Materials' Equipment and Process Integration Center (EPIC) in Santa Clara, CA.
 Figure 1. Memory device processed through two levels of copper interconnect and aluminum bonding pad in Applied Materials' EPIC facility. |
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"Memory devices are extremely sensitive to leakage, so building a memory chip verifies definitely that the process will work with microprocessors," according to John Egermeier, director of operations at the EPIC facility. Wafers from Taiwan were patterned at the EPIC center, which put in trenches, connected copper to tungsten plugs, put on a dielectric stack, built in another layer of copper wiring, and then added aluminum bonding pads. Mosel has not indicated its plans for the memory device.
 Figure 2. Copper connects to tungsten plugs in SDRAM device. |
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The EPIC center has run more than 200 lots of wafers, either with copper or copper and a low-k dielectric, on a 0.25µm process, according to Egermeier. Some users have done integrated demonstrations with test wafers going down to 0.13µm. He says Applied plans to add other modules to the facility beyond the current copper module, which provides an integrated process for copper interconnects.
So far, Cu has been used in place of Al to speed up high-performance microprocessors. But increasingly, processors are being combined on application-specific ICs (ASICs) with other types of circuitry, including SRAMs and sometimes DRAMs (dynamic memories). In such cases, it would be worthwhile to use copper for all the interconnects on a layer to minimize process steps. — B.H.
IBM, AT&T, Motorola to team for x-ray work
Three leading researchers of x-ray lithography will team up in a private effort aimed at determining whether x-ray will ever be a feasible production technology. IBM, AT&T, and Motorola will share knowledge and resources in a "CRADA-like" program that will also include Loral Corp., the 1993 buyer of IBM's Federal Systems Divison, which held much of IBM's x-ray process knowledge.
Although the three semiconductor houses and the federal government have all spent many years and millions of development dollars on x-ray, there are still a number of potential unsolvable problems, such as mask-making ability and the economics of using synchrotron light sources. One manager involved in negotiating the collaboration noted that if no robust platform is in place in the next couple of years when early 0.18-micron development must begin, "We will really have to ask ourselves what we're doing. X-ray has been a drain on the funding community for more years than it should have been, and we've got to answer the question: Is this real or not?"
Sources indicated the deal will be structured like a federal Cooperative Research and Development Agreement (CRADA), with specific milestones that must be met. Evaluation and development work will be conducted at multiple locations, including IBM's Advanced Lithography Facility (ALF) in East Fishkill, NY, AT&T's Murray Hill, NJ, facility, and university sites, including the Center for X-ray Lithography (CXrL) at the University of Wisconsin. IBM's ALF, where its compact synchrotron is located, will be the focal point for exposure work, while much mask and resist work will take place at Murray Hill.
No additional government funding will be provided to the group. All have received some level of federal contracts for their work, particularly IBM. Government officials expressed enthusiasm for the team effort, as it should help disseminate taxpayer-funded knowledge more widely. — P.N.D.
TECH BRIEFS
ASM Lithography's presentation during the recent SG Cowen investors' conference in Boston showed its technology roadmap to educate the non-litho-oriented audience. The document of course extended to 193nm...followed only by "post-193." The 157nm generation, which has gotten good buzz in recent months, was not separated out as a sure thing or even as an especially strong possibility to immediately follow 193, but lumped together with EUV, SCALPEL, x-ray, etc. Also, ASML celebrated a milestone when it shipped its 100th step-and-scan system, a PAS 5500/700 deep UV tool to Taiwan Semiconductor Manufacturing Co. in Hsinchu, where it will fabricate devices with design rules of 0.15µm and below.
Researchers at the CEA-LETI research facility in Grenoble, France, have produced functional MOS transistors with 20nm n-channel gate lengths, half the previous record, and estimated channel lengths of just 4nm. The work was done on the facility's $150 million 200mm processing line; the transistor is in line with those forecast in the SIA Roadmap for 2015 to 2020.
Forget about silicon; think spinach. Researchers at Tennessee's Oak Ridge National Laboratory have been exploring the use of spinach's protein structures as electronic switches. According to a recent issue of Gold News (published by The Gold Institute), these researchers have found a way to attach the protein structures to a gold-plated surface and align them in certain directions — "the first step towards producing simple electronic switches," the report said.