Etec five-year effort may result in direct-write lithography offering
10/01/1999
Etec Systems Inc., Hayward, CA, will develop multicolumn electron beam equipment for both mask production and direct write-to-wafer applications under a $14.2 million contract from the Defense Advanced Research Projects Agency through the Space and Naval Warfare Systems Center.
The contract is part of a three-year cost sharing agreement that will provide about $28 million to Etec for the project; a company spokesman declined to comment on the total cost of the multibeam development project, which is aimed at producing an e-beam system with much higher throughput than today's single-column systems. The spokesman said a variety of configurations are under consideration; the tools could have from five to 15 separate columns, and be usable on sub-100nm design rule projects. They are based on a "microcolumn," far smaller than current beam columns. The project will take advantage of the presence of a small group of former IBM researchers, who joined Etec last year following the company's acquisition of multibeam e-beam technology from the computer giant. If the technology proves to be commercially viable, products would likely appear about five years from now, said the spokesman.
Maskwriting applications for the multibeam system are very much in Etec's mainstream business; the improved throughput could allow e-beam tools to compete more closely with laser-based tools for volume production work. The direct-write aspect of the deal is primarily driven by Defense Department requirements for high-performance, low-volume devices for specialized military applications; a maskless litho approach provides an extra measure of security. In a recent interview, when asked whether Etec might pursue e-beam as a next-generation lithography alternative, CEO Steve Cooper commented, "Is there a niche for direct write? There might be at some point - that's one reason for developing the microcolumn. But we provided about 15 direct-write vector scan systems for the [Defense Department's] VHSIC program, and we lost a lot of money, although some of them are still running."
Cooper added that Etec is spending some 25% of revenues on R&D, while maintaining alliances with groups studying all the potential next-generation litho processes. "NGL is an extremely expensive venture...a high-risk proposition. The industry is so tied to optical, and it can ride the development activity in optical resists. There are a lot of reasons, if you can possibly extend optical, to stay with it."
Also participating in the multicolumn project are Shipley Co., which will provide assistance in resist development, and researchers at the Oregon Graduate Institute, who will work on sources and optics. Teams at Stanford University, the Naval Research Lab, and the University of Texas are also taking part.
Motorola plans heavy NGL mask investment;
EUV and e-beam capabilities in development
As part of a corporate program to develop advanced maskmaking capabilities for next-generation lithography (NGL) processes, Motorola has made strides in both extreme UV and projection e-beam reticles, and plans significant investment in both fields.
"We continue to move ahead aggressively," said Joe Mogab, manager of advanced process development. "We believe we will need NGL in the next five years or so, and we believe there is an obligation for the industry in general to do the kinds of development we're trying to stimulate here." He said that while outside funding would be considered, "It's strategic for us to be competent in masks...we know from our work in x-ray that it is the weak link. It's enabling, a must-have, and it always lags.
"Motorola is working on several fronts - through the EUV LLC consortium with partners Intel and AMD, as well as several National Labs; through its Semiconductor Products Sector R&D unit, and through Motorola's corporate physical sciences research lab in Tempe, AZ, which conducts advanced mask development. The company has already succeeded in producing a full-field e-beam projection mask on a 200mm silicon nitride wafer membrane, and a full-field EUV mask on a silicon substrate fabricated at the EUV LLC's National Lab facilities. A Leica VB-6 pattern generation tool was used for both projects.
For the e-beam mask, a good deal of the production process is derived from Moto's past x-ray work, with adjustments to the proportions of the membrane and heavy metal pattern, which scatters electrons. A patented etch process, developed by Motorola in the last few years, is used to open the membrane on the wafer. Mogab said the design was "fairly generic," rather than being tailored to the different projection e-beam technologies being developed through consortiums led by Lucent Technologies and IBM. Talks to establish a common mask format are under way; Mogab said, "It wouldn't surprise me if Motorola got involved, but we have not been invited to date." Details of the anticipated transfer of e-beam mask technology to commercial sources are still being worked out.
On the EUV side, the exotic structure of the reflective mask (up to 80 layers of material, each only 25 to 40 angstroms thick, with near-perfect inter-layer interfaces and near-perfect flatness) means that prior experience is of much less value. "The act of putting a pattern on top [of the substrate] can jeopardize its integrity," noted Mogab. He said that all EUV LLC members are cooperating on patterning work; dry etch of the experimental full-field microprocessor mask was done at Motorola. It featured an 84mm2 field, with minimum printed features of about 150nm.
In order to avoid problems with expansion from heating, the silicon substrate is to be supplanted by a new glass from Corning, which has a coefficient of expansion "a factor of a few less than fused silica - about 0.5ppm," said Mogab.
While Mogab said his group sees no show-stopping issues, and feels confident that an NGL technology will be usable in the 2004-06 time frame for sub-100nm production, he did caution that there is a long road ahead to make either method production-worthy. For both EUV and e-beam, "We're just embarking on defect inspection and repair...can you do defect inspection at a wavelength longer than the exposure wavelength? If not, we need a whole new kit of toolsellipseThe next step is to come to grips with image placement, control, defect density, inspection, and repair, so that we can bring the whole assembly [to] the state of being defect-free."
Technique brings more certainty to mask measurements
Patented flux-area measurement, which enables measurement of features <1/5th the wavelength of light being used (visible or UV), achieves accuracy <10nm and repeatability <4 nm on defects from 0.1-0.8µm, and achieves similar results with linewidth measurements. The technique is being heralded as "providing a new level of certainty to mask measurements for at least the next three generations of photolithog raphy processes," according to its inventor Peter Fie kowsky of Automated Visual Inspection (AVI), Los Altos, CA (www.aviphotomask.com).
Briefly described, the flux-area technique removes the background around a feature, then sums the total flux of light absorbed or transmitted by the feature. The flux is proportional to the area of the feature being measured. Small defects are described by the circular diameter corresponding to that area, and linewidths are computed by dividing the area by the length of the region measured:
- An image is acquired by digitizing a video image directly from an existing microscope, reticle inspection system, or metrology system.
- A reference image is developed using image processing to subtract the background from the image, leaving an image of only the defect or line to be measured.
- Total light flux from the defect image is summed in a region big enough to include 99% of the light diffracted by the features' edges.
- The measured flux is divided by the video contrast between clear and opaque, giving the feature's area in square pixels.
- The feature's area is converted to µm2 by multiplying by the magnification of the microscope if known or by comparing it to the area of a known feature, such as a 1µm defect or line.
- The area is converted to an equivalent diameter for small defects or linewidth for lines.
Fiekowsky says, "This process takes <1 sec after the user clicks on the defect. Furthermore, repeatability and accuracy exceed that attainable from SEMs because it intrinsically measures area and the quality that affects printing - the amount of light passed, rather than the relative positions of edges. This measurement readily correlates to lithography printability."
 Figure 1. Flux area measurement repeatability over 5 minutes. An I2 defect on a DuPont Verimask 845 is measured on a KLA 351 reticle inspection system in review mode. |
Tests have shown that flux area measurement repeatability of 1.1nm is typical for defects of this size. "Variability of 0.5% of the feature size is expected due to illumination variations, thus larger defects exhibit larger measurement variability," says Fiekowsky (Fig. 1).
In tests of accuracy, flux-area measurements showed a mean deviation of 7nm from the process offset of 33nm, compared to a measured mean deviation of 44nm provided with the Verimask (Fig. 2).
Fiekowsky notes, "SEM measurements to determine how much of the flux-area's 7nm variation was due to measurement errors and how much due to physical size variations were inconclusive. The SEM yielded 10-20% more deviation than the flux-area measurement, with approximately half that deviation coinciding to the flux-area measurements. The acid test for mask metrology is comparing mask measurements to SEM measurements on the resultant wafer. These measurements have not yet been performed."
In production applications, flux-area measurement repeatability can be limited by:
- magnification stability, which requires a good autofocus mechanism or optics that are not subject to magnification variation;
- illumination stability, which must be constant between illumination calibration measurements and the test measurements;
- vibration in the image, which is reduced by averaging multiple measurements;
- dirty optics, which is reduced by cleaning and field correction; and
- image distortion, which can be reduced by performing all measurements at the center of the image on the optical axis.
In addition, complex geometry near the measured feature makes it difficult to eliminate the background. In these cases, reference images of similar parts of the mask are used. However, using reference images reduces accuracy due to microscopic imperfections in the reference image.
With this technique, features smaller than 1/5th the wavelength of light are very hard to find and are often washed out by edge roughness and optical imperfections in the optics or the mask. Features larger than 1.5x the wavelength are usually measured with conventional edge-to-edge techniques because these techniques are not as sensitive to illumination variation. - P.B.
New material for cleanroom ESD control
A new line of inherently dissipative polymer alloys - commercially available in both sheet and compound forms as trademarked Stat-Rite S-Series from BFGood rich Performance Materials - promises to ease electrostatic discharge (ESD) problems in semiconductor manufacturing cleanrooms. (The material is also applicable in component packaging applications.)
These materials are two orders of magnitude lower in surface resistance (108Ω) than existing electrostatic discharge control technologies. The net results are rapid, consistent, and predictable static decay times that remain intact from the polymerization stage through compounding and processing, whether thermoformed, injection molded or extruded. In addition, these new alloys show significantly decreased static decay times of below 0.1sec (from 1000V).
The polymer alloys are applicable to cleanroom fixturing and surfaces because they exhibit lower ionics, lower offgassing, and lower tribocharging than currently used materials. In addition, the discharge characteristics are not dependent on relative humidity. These attributes minimize the potential for particle and corrosion problems in addition to damage from electrostatic discharge.
Neil Hardwick, marketing manager at BFGoodrich Static Control Polymers, explains, "Until now, designers had to choose between conductive fillers like carbon, which is unable to consistently meet a surface resistance above 104Ω, and alloys or antistats, which are unable to provide a surface resistance below 1010Ω and 1012Ω, respectively."
108Ω is the optimum target for surface resistance. At 104Ω and below, objects discharge too quickly and damage nearby components via an unpredictable ESD event. At 1010Ω and above, slow static decay times can result in latent charges.
"We've done something that no one else in the industry has been able to do," says Hardwick. "By concentrating on the earliest stage in the production process - polymerization - and increasing the charge carriers available, we've created a new generation of inherently static dissipative polymers that will gives a new confidence in ESD control." - P.B.
European solar-cell efficiency record
Using an Aixtron MOCVD system, researchers at the Fraunhofer Institute for Solar Energy Systems (ISE) have grown gallium arsenide (GaAs) single-junction solar cells with 24.2% conversion efficiency, reportedly a European record and close to other efforts in the world. GaAs solar cells are preferred for powering spacecraft.
Briefly described, the structure is an active GaAs single junction solar cell grown on an inactive AlGaAs/GaAs backside on a GaAs substrate. It is capped with an AlGaAs window. The reflectivity of the backside is approximately 70% for light with energy close to the bandedge of GaAs. The cell is coated with a TiO2/MgF2 antireflection coating.
ISE plans to develop this process further, targeting the production of GaInP-GaAs tandem solar cells grown on germanium (Ge) substrates. The group's engineers believe conversion efficiency can be further increased with GaInP-GaAs. In addition, Ge substrates reduce weight significantly and are resistant to cosmic radiation.
Interestingly, ISE engineers believe their high efficiency solar cell technology can be used for terrestrial applications if they are applied with "300 to 1000 suns" concentrators. - P.B.
SEZ, AlliedSignal seek alternative to copper CMP
In an alliance that could add a twist to the copper CMP roadmap, AlliedSignal and spin processing toolmaker SEZ are developing an alternative CMP process for advanced copper interconnects.
Specifically, the two companies are developing an etch method for removing copper films; the goal is to remove copper films with the same results as CMP but with no risk of damage to low-k materials in the structure. The project is incorporating chemistries and low-k materials from AlliedSignal's Electronic Materials unit and SEZ's spin processing systems, said Michael West, SEZ business and strategic technology director.
West noted that new equipment will not need to be developed, but a fine-tuning of AlliedSignal's chemistries and SEZ's tooling is on tap. Much of the joint work will be based at AlliedSignal's low-k integration facility in Sunnyvale, CA, where an SEZ Spin-Processor 203 (200mm platform) system has been delivered. SEZ also has a full-time process engineer at the integration site.
The firms expect to show full feasibility of the method in 1Q00, and begin beta site testing thereafter, said West. Joint marketing of the process is also planned. If successful, the project will allow SEZ to expand its frontside wafer processing offerings while also giving it a significant opportunity in the copper planarization market.
The companies said chemical etch planarization is an attractive alternative to CMP because it does not involve the mechanical downforce of CMP. Mechanical downforce in CMP can damage porous low-k films, which are targeted for use in many advanced dual damascene interconnects.
While a complete cost-of-ownership study must be undertaken, West noted that the etch process may offer savings when compared to CMP, as the need for consumables and a post-CMP clean step is eliminated.
SEZ has been pursuing this technology for "quite some time," said West, who noted Samsung developed a similar process using an SEZ system for CMP of tungsten plugs. For AlliedSignal, the work is part of its overall effort to offer complete interconnect solutions; the company has rolled out a number of spin-on low-k materials, including organic, inorganic, and inorganic/organic hybrid films. The joint effort with SEZ, however, "does not reflect an abandoning of CMP," said a company spokesman. The firm is continuing to explore CMP/low-k integration issues. Said the spokesman, "There are as many (process) choices as there are customers."
- C.L., J.A.
TECH BRIEFS
A collaboration between Trikon Technologies (Newport, UK), the manufacturer of PVD, CVD, and plasma etch systems, and the Resist Test Center of International Sematech (Austin, TX) has produced trenches 25nm wide. This work follows the successful creation in June of 30nm semiconductor contact holes. The trenches were produced using an advanced DUV 193nm CARL photoresist system developed by researchers at Infineon Technologies in Erlangen, Germany. This system includes a unique chemical biasing step for definition of very small trenches and contact holes. Photolithography was performed on a 0.60 NA, 193nm microstepper, using a standard binary reticle. Etch processes were carried out on Trikon's OMEGA plasma etchers, using ICP and MORI plasma modules.
An industry-academic research team in South Korea has developed a new high-performance wafer for production of devices beyond the 256Mb DRAM generation. Dubbed the "Super Silicon Wafer," the 200mm substrate is designed to improve device yields by offering a defect-free active area for device fabrication, and a reduction of heavy metal contaminants to less than 1ppb through the use of high-density oxygen precipitates. Samsung Electronics worked with a team led by Jea-gun Park at Hanyang University on the project; patents are being sought and the group is seeking license agreements (and a revenue stream) with Japanese wafermakers including Mitsubishi Materials. The Super Silicon Wafer is seen costing about 40% less than epi wafers, while offering improved performance. Plans call for an extension of the manufacturing technology to 300mm sizes.
Cross-sectioning capability enhances SEM contrast and definition
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A new process addition to the in-fab ion-milling cross sectioning capability of FEI, Hillsboro, OR, dramatically enhances contrast and defines material interfaces between layers in SEM images. Dubbed Delineation Etch, the new etchant gas interacts with the focused ion beam to create topography on a cross-sectioned surface based on different etching rates of the materials present. The process uses a proprietary etchant gas that, unlike xenon difluoride, is nontoxic and does not spontaneously etch silicon. (This SEM image compares unetched and Delineation Etched regions on the same sample.) "The results are equivalent to a mechanically prepared cross section with wet etch and can be obtained in the fab in a fraction of the time. Previously, FIB cross sections were unable to deliver this kind of detailed interlayer information and samples had to be taken outside the fab for mechanically polished and wet-etched cross sections," says Jay Lind quist, VP of technical marketing. (Source: FEI Company; Delineation Etch is a trademark of FEI) -P.B.