In situ wafer temperature measurement during plasma etching
10/01/1999
Wafer temperature is one of the hidden parameters in plasma etching that has a significant impact on process results and can cause variation between presumably identical process tools. Many conventional measurement techniques have limited sensitivity, but there is a new tech nology for in situ direct monitoring. It has provided new insights into plasma process behavior and identified process parameters that affect wafer temperature.
Monitoring wafer temperature in plasma etching is a significant challenge, given the harsh plasma environment. Yet controlling temperature is essential, since it significantly affects process results. Careful monitoring can minimize variation, allow a wider process window for other parameters, and improve process control. For example, resist-masked etches at high power (such as pad-etch through a thick dielectric) and at high temperature (such as aluminum-copper alloy to eliminate low-volatility copper residues) are difficult to optimize. But with direct wafer temperature measurement capability:
- Resist temperature can be kept below the flow point to improve process results without compromising the resist [1].
- Sidewall profiles can be better controlled to avoid sloping at low temperatures or undercutting at high temperatures [2, 3].
- Gate oxide damage can be minimized by reducing temperature during plasma processing; as wafer temperature increases, it takes less charge for oxide breakdown to occur [4].
Conventional temperature measurement techniques, such as temperature-sensitive decals, have limited temperature resolution and only provide a single measurement of peak temperature, which may not necessarily coincide with the process peak. Fortunately, a new technology for real-time in situ monitoring of actual wafer temperature has been developed. It allows monitoring of temperature over time and provides better understanding of the entire thermal cycle.
Pad-etch baseline process
Our goal was to understand the impact of various process parameters on wafer temperature and the implications for process results. We began with a standard pad-etch process as a baseline, then varied a number of process parameters and observed their effect on both wafer temperature and the process. Parameters evaluated included power level, backside He cooling pressure, electrostatic chuck voltage, and flow rates of CF4, CHF3, SF6, O2, and Ar.
We used a Lam Rainbow 4520 dielectric etcher with a helium-cooled bipolar electrostatically clamped wafer chuck (ESC). We studied passivation etching of openings over bonding pads, monitoring temperature in situ in real time using a 200mm bare silicon wafer with phosphorescence-based fiber optic probes embedded in the silicon at four points across the wafer diameter: center, ~3mm from the edge, and two points equally spaced in between [5].
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The sensors are temperature-sensitive phosphor coated onto the surface of channels in the silicon wafer. Optical fibers are aligned with the temperature-sensitive phosphorescent material at each sensing location inside the wafer. This optimizes the thermal contact of the sensor with the wafer and minimizes temperature offset. Light pulses activate the phosphor. Then an instrument measures phosphorescent decay time, which is dependent on temperature. From the wafer, the optical fibers pass through a vacuum feedthrough (i.e., an aluminum insert that converts the etcher viewport). Because they are electrically inert, the fiber optic temperature sensors are not affected by plasma.
We collected temperature measurements from the four locations on the wafer at one-second intervals, recording the temperature profile vs. time during plasma etch using a data acquisition system and data analysis software furnished with the monitor wafer.
The repeatability of the temperature measurement is ±0.75°C, if sufficient time is allowed for the wafer temperature to stabilize. The response time is a fraction of a second after a process change. Stable temperatures are typically achieved within ~20 sec.
Our baseline pad-etch process uses a fluorocarbon-based chemistry to etch bond pad openings through SiN over the SiO2 dielectric passivation layer: 400 mtorr, 1400W, 1.25cm gap, 600V ESC, 400 sccm Ar, 60 sccm CF4, 15 sccm CHF3, 10 torr backside He pressure, and 40°C and 20°C top and bottom electrode temperatures. After this 260-sec step, we added SF6 (20 sccm for 15 sec) to etch through the TiN and stop on the AlCu. This enables wire bonding to AlCu pads.
It is significant to note that at this point in the process, the wafer has its highest value, and losses at this step are costly to manufacturing.
 Figure 1. Four-point temperature measurements from the baseline pad-etch process. |
Our first observation was the change in temperature when SF6 was added during the TiN etch step. The edge temperatures increased and center temperatures decreased (Fig. 1).
Keeping top and bottom electrode temperature setpoints at 40 and 20°C, we made changes to the baseline process, holding each process condition for 45 sec (Fig. 2). For most of these process changes, temperatures stabilized within ~20 sec after making the change. We observed that varying process conditions while keeping the lower electrode temperature setpoint constant at 20°C resulted in a 45 to 162°C average wafer temperature. With no He cooling flow, the wafer edge quickly reached ~180°C. Temperatures above ~120°C will cause photoresist to flow and distort resist patterns. Resist reticulation or burning would certainly occur at or above 180°C.
 Figure 2. Temperature measurements with variations on baseline pad-etch process. |
We kept the plasma on continuously throughout the experiments in Fig. 2. In three cases noted, however, the plasma aborted because some parameter such as chamber pressure was unable to stabilize within the prescribed 7 sec. The process was restarted at the same point after conditions had stabilized. The aborts appear to have had no impact on the results since the standard process temperatures repeated as expected (the dashed line in Fig. 2).
To better compare the effects of process changes in the remaining figures, local average temperatures were calculated based on the last three stable points measured (the last 3 sec) prior to a subsequent process change. Opening and closing gas valves caused temperature spikes of several degrees as gases burst into the chamber and caused transient pressure changes.
Process observations
We found that temperature measurement repeatability, determined from repeated baseline measurements, was quite good except for the initial first plasma-on step; the temperature had not completely stabilized during the 45-sec Step 4 (see table). Overall, standard condition temperatures repeated within ±0.75°C (±1.4°C, including Step 4).
Because the lower electrode temperature setpoint was held at 20°C, it is clear from the data in the table that the baseline pad-etch process resulted in a wafer temperature rise of about 40°C (final 60°C wafer temperature) with a systematic 15°C temperature nonuniformity across the wafer. This is true even though the etcher is equipped with a state-of-the-art ESC and He backside cooling.
We found that many process parameters had little effect on wafer temperature, including varying fluorocarbon gas flow rates, oxygen flow rate, chamber pressure, or inter-electrode gap differences. For all of these changes, the temperature varied <±1.5°C.
 Figure 3. Effect of Ar flow rate variations. |
Ar had a large effect on temperature, however (Fig. 3); Ar cools the wafer and improves temperature uniformity across the wafer. Presumably this is because Ar stabilizes the plasma by more readily transferring energy from electrons to neutral gas molecules (via Penning ionization [6]), thereby improving plasma uniformity.
 Figure 4. Effect of SF6 gas flow variations. |
We found that SF6 exhibited unique behavior when added to process gases (Fig. 4). Wafer temperature uniformity changed as SF6 was added, with edge temperature climbing steadily until temperature variation across the wafer approached 30°C. Away from the extreme edge, the temperature change with SF6 flow was not monotonic as shown - near-edge and center temperatures actually crossed over as SF6 was added, then crossed over again as it was increased.
This effect was repeatable and is probably related to the strongly electronegative behavior of SF6, which holds its electrons so tightly that igniting and sustaining a plasma is difficult. If neutral gas molecules do not release their electrons, then the electron cascade required to transfer RF energy into the neutrals cannot be maintained. The result is that SF6-based plasmas sustain more nonuniformity than plasmas composed of other gas species. The plasma nonuniformity probably translates into the wafer temperature nonuniformity observed in this study. Another study found that small changes in SF6 content in the plasma affected discharge parameters, plasma uniformity, and electron temperature [7].
 Figure 5. a) Effects of RF power variations, b) wafer cooling by varying ESC voltage, and c) wafer cooling by varying He cooling pressure. |
Wafer temperature increased as we raised RF power (Fig. 5a) or as wafer cooling degraded by decreasing either electrostatic chucking voltage (Fig. 5b) or backside He pressure (Fig. 5c). When wafer cooling was less efficient, it took longer to reach thermal equilibrium (Fig. 2), most notably when He cooling was turned off (i.e., temperature did not fully stabilize even in 45 sec). The He cooling pressure effect was substantial.
Without He cooling, wafer temperature soared to ~162°C, and within-wafer nonuniformity reached 34°C, with the maximum temperature at the wafer edge ~180°C. Further reductions in wafer temperature and nonuniformity may be possible by increasing He pressure above 15 torr (Fig. 5c). This was unexpected, as commonly used backside He pressures are usually no higher than 8-15 torr.
Process findings
Our key findings from this study are:
- Even with an ESC and He cooling, turning the plasma on resulted in a 40°C increase in wafer temperature. For a 20°C setpoint on the lower electrode (i.e., wafer chuck) the actual wafer temperature was ~60°C for the baseline etch process.
- Process variations alone, without changing the 20°C lower electrode setpoint, caused wafer temperature to vary from 45 to 162°C.
- Center-to-edge temperature variation was ~15°C, but process changes caused this to vary from 9 to 34°C.
- Wafer temperature increased as power was raised or as wafer cooling was degraded by decreasing backside He pressure or ESC clamping voltage. With less efficient wafer cooling, it took longer to reach thermal equilibrium. Increasing He pressure to 15 torr improved cooling efficiency.
- Varying the flow rates of fluorocarbons (CF4 and CHF3) and of O2 had relatively little effect on temperature. Chamber pressure and interelectrode gap also had an insignificant effect on wafer temperature.
- Ar flow rate had a greater effect on temperature and improved temperature uniformity across the wafer, presumably because the plasma density uniformity was enhanced.
- Wafer temperature uniformity changed as SF6 flow increased, but not monotonically with flow; near-edge and center temperatures crossed as SF6 was added, then crossed again as flow increased further.
- Opening and closing gas valves caused temperature spikes of several degrees as gas bursts into the chamber caused transient pressure changes.
These significant observations on the effects of wafer temperature during plasma etch were made with just a few hours of work. Most of this understanding could not have been achieved with conventional temperature measurement techniques, such as temperature sensitive decals, which have limited temperature resolution, record only the maximum temperature reached, and can contaminate the process chamber.
At VLSI, we will apply our new understanding of the impact and interaction of various parameters on wafer temperature for pad etch by considering process recipe modifications. For example, as we continue to study the data, He pressure, Ar flow, SF6 flow, and power levels may be optimized and monitored more closely. Many plasma etch processes can benefit from an understanding of real-time wafer temperature. In extreme cases, plasma-off steps may need to be added to long, temperature-sensitive processes to allow wafers to cool.
Conclusion
We have found that an in situ embedded-probe wafer temperature measurement system is useful for hardware matching, qualification, and periodic monitoring of wafer temperature in plasma etchers. Repeatability and response time are very good. The real-time nature of the system makes it particularly well-suited for plasma etch process development, allowing wafer temperature to be considered and developed into the process, even when there are multiple plasma-on steps.
Clearly, knowing the lower electrode temperature setpoint does not translate into knowing the actual wafer temperature in a plasma environment. Understanding and controlling the actual wafer temperature - as opposed to simply controlling the temperature setpoint of the wafer chuck - is critical for preventing resist burning, controlling vertical and lateral etch rates of temperature-sensitive films (such as AlCu or organic polymers), and minimizing the effect of charging damage on gate oxide.
Acknowledgments
This work was accomplished with the help of Chris McDowell at VLSI Technology Inc.; Todd Preece at Lam Research Corp.; and Steve Munoz, Lisa Jones, and Jerry Harmon at SensArray Corp.
References
- J. Hackenburg, B. Holbrook, T. Ingwersen, Proc. 7th Symp. Plasma Processing, Electrochemical Society, Pennington, NJ, pp. 317-325, 1988.
- M. Haverlag, G.S. Oehrlein, D. Vender, J. Vac. Sci. Technol. B, 12 (1), pp. 96-101, Jan. 1994.
- O. Krogh, R.N. Carlile, R.N. Nowlin, Plasma Chemistry and Plasma Processing, 10 (2), pp. 231-246, June 1990.
- S. Ma, J.P. McVittie, J. Vac. Sci. Technol. B, 14 (1), pp. 566-570, Jan. 1996.
- SensArray Corp., Santa Clara, CA.
- B. Chapman, Glow Discharge Processes, John Wiley & Sons, New York, p. 44, 1980.
- K. Aoyagi, et al., Jpn. J. Appl. Phys. Part 1, 36 (3A), pp. 1268-1273, March 1997.
Calvin T. Gabriel received his BS (ChE) from Northwestern University, his MS (ChE), and engineer's (ChE) degrees from MIT, and his MS (EE) from Stanford University. He is an engineering fellow leading plasma etch development at VLSI Technology Inc., 1109 McKay Drive M/S 02, San Jose, CA 95131; ph 408/434-3158, fax 408/922-5393, e-mail [email protected].
Edward K. Yeh received his BS (ChE) from UCLA and his MS (ChE) from UC Berkeley. He is a process development engineer working on dielectric etch development at VLSI Technology Inc; ph 408/474-5429, fax 408/922-5393, e-mail [email protected].
Calvin T. Gabriel, Edward K. Yeh, VLSI Technology, San Jose, California