Isolation's path to SOI technology

10/01/1999

While CMOS silicon-on-insulator clearly results in improvements in device physics and electrical parasitics, its application has to address issues associated with using this material substrate, including changes, although minor, to several wafer fabrication processes and modified CAD tools. Manufacturers pursuing this route need to ask: Are the added R&D costs and the overall improvement in performance cost effective compared to standard bulk-silicon or epitaxial-based VLSI CMOS technology? The answer is rather complex and is intimately linked to the final IC. The technology of choice will be the one that provides the desired function at the lowest cost.

Figure 1. Cross section of an advanced VLSI CMOS IC.Click here to enlarge image

Most VLSI CMOS ICs are fabricated on silicon (Fig. 1) using five different types of isolation (see "Types of isolation for standard CMOS VLSI" on p. 111). To visualize the importance of isolation in semiconductors, consider a VLSI circuit with one million transistors. If each transistor produces 1nA of off-state leakage current, the total stand-by power dissipation would be several milliwatts, which is intolerable for many consumer and portable applications.

During the lifetime of ICs since 1958, silicon planar technology has become the dominant semiconductor technology and many isolation technologies have been developed. The various types of isolation present different design and performance challenges.

Because isolation in semiconductors is complex and needs to be described within context of the particular technology being used, here we focus on technologies used in VLSI CMOS silicon ICs that may be used in telecommunications applications designed with both analog and digital circuitry.

Intra-device isolation

The field of intra-device isolation is quite extensive with a unique set of major issues that face device physicists, technologists, and circuit designers.

The p-n junctions of a MOSFET are reverse-biased and essentially no current flows in the diode. Typical leakage specifications are 1 x 10-9 A/cm2. Crystal defects within the space charge layer of the diode that are decorated with mid-band-gap state metals can cause individual diodes to have significantly larger current leakage values. This is a major subject in the fabrication of dynamic ICs and DRAMs.

Complementary to this subject is the issue of ultra-thin oxides needed for scaled deep submicron MOSFETs. Here the quantum mechanical tunneling phenomena arises, and gate dielectrics are no longer insulators. There is extensive research being conducted in the area of alternate dielectrics with very high dielectric constants. The goal is a film thickness that adequately suppresses quantum mechanical tunneling, while still allowing the MOSFETs to possess the required drive currents.

Inter-device isolation

In the layout of an IC, a significant amount of space is allocated for adequate electrical isolation between individual MOSFETs. To reduce this overhead, major advances in isolation have been pursued. Presently, advanced techniques, such as shallow trench isolation, are used in leading-edge silicon ICs.

Intra-tub isolation

Silicon substrates provide the mechanical support for planar VLSI ICs. In addition, since all junctions to the substrate are designed to be reverse-biased, the tub or substrate, to first order, acts as an isolating equipotential plane among the different components within the IC. However, the substrate is not a perfect isolator, hence both parasitic AC and DC currents flow within it due to its finite conductivity. The parasitic p-n coupling capacitance and leakage currents can give rise to additional circuit problems such as crosstalk and signal corruption. VLSI circuits that are very sensitive to noise and leakage currents, such as analog designs, imaging devices, and DRAMs, require careful circuit design and materials processing.

Additional circuit problems such as overloading of on-chip substrate bias generators, threshold voltage variation due to changing substrate potential, drain-source breakdown, excess minority carrier, photon generation, DRAM refresh time, and device degradation are directly related to the amount of substrate current generated in the circuit.

Inter-tub isolation

VLSI CMOS circuits require carefully engineered substrate doping profiles. Inter-tub coupling can be caused by the resistive voltage drops induced by ground currents, as well as by voltage transients. Both higher packing density and higher frequency of operation cause these effects, aggravating circuit problems.

The traditional solution to circumvent these types of problems has been to use silicon wafers with an added epitaxial layer - a few microns of boron-doped (~2 x 1015 atoms/cm3) silicon grown on top of a p+ substrate (1 x 1019 atoms/cm3). The doping concentration and the thickness of the epitaxial layer can be carefully controlled, and it can be made free of unwanted impurities, primarily oxygen and metals. Thus, the device physics and structures can be successfully controlled. Further, the p--p+ substrate provides damping of substrate voltage transients and reduction of unwanted minority carriers in the substrate.

Epitaxial layer thickness is dictated by the particular wafer-processing thermal budget, which drives boron from the heavily doped substrate into the epitaxial layer, reducing its effective thickness. In a high-energy-implant (HEI) tub process, where the tub profile shape is determined by a series of ion implants, the long high-temperature tub drive is eliminated, thus allowing use of thinner epitaxial silicon [1].

Latchup between p-n junctions in neighboring tubs is a major concern for all VLSI CMOS devices. The result of latchup is a state of heavy conduction (i.e., a short) between VDD and VSS power lines. Once latchup occurs, the power supply must be disconnected to stop it. This also results in the loss of any information that is dynamically stored within the circuit.

Figure 2. Two transistors in neighboring tubs, and the parasitic npn and pnp bipolars that cause latchup.Click here to enlarge image

Latchup is a well-understood phenomena and can be dealt with using proper processing and design methodologies. With the constant reduction of feature spacing, however, latchup immunity is a continuing challenge. Consider, for example, that the source-drain junctions of transistors in neighboring tubs form parasitic bipolar structures (i.e., the p+-junction, n-tub, and p-substrate produce a vertical pnp and the n+-junction, p-substrate, and n-tub form lateral npn devices). Being in close proximity, these parasitic bipolars can interact electrically to form a pnpn thyristor (Fig. 2).

An initial latchup triggering current can be induced under abnormal, although frequently occurring, operating conditions, such as fluctuation of the supply voltage or an external electrostatic event. If this induced current and the resistance of the tub or the substrate are high enough, a sufficient IR drop can be developed to forward bias the emitter-base junction of one of the parasitic bipolars. Then the collector current of one parasitic bipolar supplies base current to the other, in a positive feedback arrangement that can result in a sustained "latched" current mode (i.e., the "on" state).

The relevant device components in latchup, in addition to the parasitic bipolars, are the resistances of the substrate in both the n- and p-tub regions. Hence, an effective technique for suppressing latchup is to reduce tub and substrate resistances using either an epitaxial substrate [2] or a HEI retrograde tub, or both. Another widely used technique is to reduce voltage drops in the substrate by the placement of grounding "guard ring" diffusions around sensitive input-output circuits.

Substrate crosstalk

Coupling through the substrate is an important limiting factor in mixed-mode, high-frequency ICs. In such mixed-signal systems, fast-switching transient current spikes produced in the digital circuit can couple into sensitive analog components and limit analog precision. This problem becomes more severe as clock rates increase, circuit features shrink, and end-user applications, such as analog to digital (A/D) and D/A converters, mobile communications products, voice-band coder-decoders (CODECs), and video DSPs, demand greater precision from the analog circuitry.

Several methods, such as a low-inductance substrate, increased physical separation, and guard rings, have been proposed for reducing substrate noise [3]. In addition, separation of analog circuits from digital circuits on the substrate can be accomplished by fabricating them in isolated tubs using silicon-on-insulator (SOI) processing [4]. This approach is effective, but not always practical because of the complex fabrication and high cost.

SOI technology

The original driving force behind SOI technology was to produce radiation-hardened ICs using an alternative to expensive silicon on sapphire (SOS), a thin film of silicon grown on an insulating Al2O2 substrate [5]. SOI uses a thin layer of silicon isolated from a silicon substrate by a relatively thick layer of SiO2.

Figure 3. n- and p-MOSFETs on SOI illustrating the silicon layer, buried oxide, lateral isolation, and floating body.Click here to enlarge image

MOSFETs in SOI do not need special junction isolation precautions (Fig. 3). The parasitic FOX transistor does not exist because the field oxide extends through the silicon film and joins the buried oxide. Together with the lateral isolation, SOI completely isolates devices.

The thickness of the silicon layer can be chosen so that MOSFETs will operate in fully depleted (FD) or partially depleted (PD) regimes. With FD, the channel depletion region extends through the entire thickness of the silicon layer. However, it is not easy to ensure the FD mode under all operating conditions.

SOI dielectrically isolates components, enabling fabrication of smaller, denser, and faster ICs. It reduces the various parasitic device and circuit capacitances, and the structures that cause latchup. In addition, it increases alpha particle immunity and reduces intra-IC crosstalk.

SOI technology is particularly attractive for low-power ICs used in portable system applications. It is also appropriate for emerging system-on-chip ICs used for smart power, microelectromechanical systems (MEMS), mixed-signal, and integrated optics applications.

SOI Material

During the 20 years since it was first reported [6], there have been many approaches to manufacturing SOI substrates, and quality and availability problems are slowly being resolved:

• Separation by implantation of oxygen (SIMOX [7]) places a high concentration of oxygen beneath the surface of a silicon wafer, typically using a dose of 2 x 1018 atoms/cm2 at 200keV. The implantation receives a high-temperature anneal to restore crystalline quality of the silicon layer over the buried stochiometric oxide (BOX), which forms during the same heat treatment. The thickness of the silicon and the SiO2 layers in SIMOX are typically 250nm and 350nm.
• The latest trend with SIMOX fabrication is to use a lower oxygen implant dose to obtain an improved, low-cost SOI material. This new approach has drastically improved the top silicon film crystalline quality, but also yields much thinner silicon and SiO2 layers. For example, the internal thermal (ITOX) SIMOX process uses a high-energy, smaller-dose oxygen implant to produce a thick silicon layer and a thin BOX layer (~300nm and 80nm) [8]. A subsequent anneal in oxygen oxidizes some of the superficial silicon layer and increases the thickness of BOX. In addition, the thermal oxide growth step improves the quality of the silicon film and the BOX.
• Separation by plasma implantation of oxygen (SPIMOX [9]) is another potentially low-cost process for fabricating SOI substrates. This is a modified SIMOX process where oxygen is implanted by plasma immersion ion implantation (PIII). The whole wafer is implanted at once; implantation time is independent of the wafer size, resulting in a high wafer throughput. A potential drawback of this technique is the lack of ion beam selection and possible contamination.
• Bond and etch-back SOI (BESOI [10]) is used to manufacture relatively thick films of both oxide and silicon. Two silicon wafers, one with an oxide layer, are bonded together using van der Waals forces. A subsequent anneal increases the bonding strength. Finally, one side of the bonded substrate is thinned ~1µm by mechanical grinding and polishing to within 10-30% uniformity. Better uniformity can be achieved with a chemical etch stop. Typically, the bonded wafers have thicker, yet better-quality, silicon and buried oxide layers compared to SIMOX.
• Smart Cut Technology [11] combines ion implantation and wafer-bonding technologies. A wafer is oxidized to form what will become the buried oxide layer of the SOI structure. A high-dose (5 x 1016 ions/cm2) hydrogen ion implantation through the oxide forms cavities or microbubbles at the implantation range. This wafer is bonded to another wafer using van der Waals forces. A 500°C thermal activation merges all the hydrogen cavities, causing the top section of the wafer to delaminate. The use of ion implantation for the layer separation improves the layer thickness uniformity over that of bonded wafers. An advantage of this technique is that the remaining wafer is reclaimed and can be re-used as a "handle" wafer.
• Relatively new epitaxial layer transfer (ELTRAN [12]) produces SOI wafers with a relatively defect-free silicon film. It is formed by growing an epitaxial layer on a layer of porous silicon. This wafer is then bonded to a "handle" wafer and is either ground down or just separated at the porous layer.

These SOI technologies are in widely different stages of maturity. Some have been used in successful processing of megabit ICs, while others are in their infancy with little or no reported IC fabrication and may not be commercially viable.

SOI lateral isolation

Traditionally, lateral isolation between SOI devices is obtained by a MESA structure or by LOCOS [13]. In MESA isolation, the active device regions are masked to etch the field device areas. The SOI oxide helps as the etch-stop layer, while anisotropic etching allows for efficient isolation scaling. The weak point of this isolation technique is the sharpness of the sidewall and its potential impact on gate oxide integrity and device subthreshold characteristics.

LOCOS isolation in SOI is much the same as LOCOS in bulk silicon. The oxidation kinetics in SOI are somewhat different, however, particularly when the growing oxide reaches the buried oxide. The oxidation times to consume the entire silicon film can be long, resulting in transistor-width loss. It is also possible that LOCOS isolation may introduce stress in the active region of the MOSFET, causing device leakage. As a result, trench isolation has become the prime choice for SOI lateral isolation (see table on p. 116).

SOI advantages

The appealing aspect of SOI technology is its compatibility with standard semiconductor fabrication, while providing many benefits.

In MOS-SOI, the junction capacitance is lower than that of a bulk-CMOS transistor. Depending on the circuit layout, the total capacitance of an SOI IC can be reduced by 15-50% compared with the same IC fabricated in bulk silicon. The wiring capacitance due to the existence of the buried oxide beneath the FOX is also slightly reduced. Operation of a multi-GHz prescalar with a 50% increase in the speed compared with those fabricated in bulk was first reported in 1989 [14]. The gain in the speed was shown to be entirely due to the decrease in the capacitance of the junctions.

An SOI MOSFET is one of the best candidates for low-power, high-speed operation. Fully depleted MOS-SOI operates faster than bulk because of the lower threshold voltage and increase in drain current. A sharper subthreshold slope allows for faster switching MOS devices, along with a reduction of threshold voltage, thereby increasing drive current at low voltages.

Click here to enlarge image

SOI can also achieve higher packing density due to smaller design rules (i.e., contact overlap, lateral isolation, and, in particular, the n+-p+ spacing).

SOI reduces the substrate-collection volume for alpha-particle-generated electron-hole tracks, hence lowering soft-error sensitivity. In particular, SOI technology for ECL bipolar-CMOS ICs is preferred because of the high sensitivity of the ECL peripheral ICs to radiation.

Dielectric isolation in SOI also helps in decoupling analog and digital components of a mixed-signal IC through reduced substrate crosstalk. For applications above 1GHz, special low-resistivity substrates may be needed.

SOI issues

Although for many years the fabrication of ICs on SOI has been recognized as very attractive, to date, the production has been limited to niche markets due to a number of technical issues that have not yet been completely resolved. These include the defect and thickness uniformity quality of the silicon layer, gate oxide yield, and Vt uniformity, as well as the quality of the buried oxide. While there have been limited quantities of SOI starting material for production, this is becoming less of an issue with the advent of several companies that specialize in offering different types of SOI wafers.

Today, the more critical issues with SOI technology are:

• Floating-body effect (FBE), which is a consequence of the complete isolation from the substrate (see Fig. 3). FBE is one of the most crucial difficulties of SOI devices that must be taken into consideration when applying SOI devices to actual VLSI ICs. FBE can lead to circuit instabilities, hysteresis behavior, frequency-dependent delay time, and pulse stretching. FBE can be dealt with by using a body contact for single devices, but this is generally not an optimum solution, due to circuit density implications and compatibility issues with IC designs intended for bulk silicon fabrication.
• Limited CAD tools for SOI IC designs that take full advantage of the packing density and electrical benefits is another serious issue impeding the introduction of this technology into the mainstream.
• Fabrication issues make the task of processing on SOI more than just a drop-in process on a new substrate. For example, interference patterns caused by thickness variation of SOI layers could bring about leveling correction error of a photolithography stepper unless a correct antireflecting coating is used. Extreme precautions have to be taken during front-end processing because of the limited amount of silicon on the top surface of an SOI substrate. This thin silicon layer can be easily removed by extensive wet or dry etches or oxidations. In addition, SOI's two extra layers and the associated interfaces make metrology a more complicated task compared to bulk silicon processing.

Conclusion

The table above, which has been extracted from SOI-related papers dealing with VLSI ICs fabricated on SOI presented at the International Electron Device Meetings (IEDMs) between 1989 and 1998, provides an indicator of SOI R&D efforts. The initial publication of the gain in the speed of a relatively small IC fabricated in SOI [14] has been followed by a series of studies of performance enhancement of larger ICs, mostly using SIMOX wafers. In general, these ICs were fabricated in PD SOI and the silicon and BOX thicknesses were all comparable and fairly thick.

While there were no large SOI ICs reported at the 1998 IEDM, presenters at the 1999 IEEE International Solid-State Circuits Conference announced fabrication of 32bit and 64bit microprocessors, and 16Mbit DRAMs on SOI; depending on the technology and circuit layout performance, 10-40% enhancement was reported. These reports indicate a new degree of maturity in SOI technology.

The differences between the physics of devices fabricated on bulk silicon and SOI result in a long, expensive learning curve in the fabrication, characterization, and modeling of acceptable SOI transistors and devices. Considerable investment of both time and capital are required to gain understanding of SOI devices and ICs, and their performance and yield. When that is combined with designs optimized for SOI, one can expect gains in performance. n

Acknowledgments

The authors thank George Celler for his technical comments. Smart Cut is a registered trademark of SOITEC.

References

1. R.A. Martin et al., "A New Process for One Micron and Finer CMOS," IEDM Tech Digest, p. 403, 1985.
2. R.S. Payne, W.N. Grant, W.J. Bertram, "Elimination of Latchup in Bulk CMOS," IEDM Digest, p. 248, 1980.
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4. J.P. Raskin et al., "Substrate Crosstalk Reduction Using SOI Technology," IEEE Trans. Elec. Dev., Vol. 44, p. 2252, 1997.
5. G.W. Cullen, M.T. Duffy, R.K. Smeltzer, "Recent Advances in Heteroepitaxial Si on Sapphire Technology," VLSI Science and Technology, p. 230, 1984.
6. K.F. Lee et al., "Thin Film MOSFETs Fabricated in Laser-Annealed Polycrystalline Silicon Films," Appl. Phys. Lett., Vol. 35, p. 173, 1979.
7. K. Izumi et al., "SIMOX Technology for CMOS LSI's," VLSI Symp. Tech. Digest, p. 10, 1982.
8. S. Nakashima et al., "Investigations on High-Temperature Thermal Oxidation Process at Top and Bottom Interfaces of Top Si of SIMOX Wafers," Jour. Electrochem. Soc., Vol. 143, p. xxx, 1996.
9. J. Liu et al., "Formation of Buried Oxide in Silicon Using Separation by Plasma Implantation of Oxygen," Appl. Phys. Lett., Vol. 67, p. 2361, 1995.
10. S.S. Iyer et al., Proceedings of the ECS Meeting on Semiconductor Si PV94-10, p. 391, 1994.
11. M. Bruel, "Silicon on Insulator Material Technology," Electronics Letters, Vol. 31, p. 1201, 1995.
12. T. Yonehara, K. Sakaguchi, N. Sato, "Epitaxial Layer Transfer by Bond and Etch-Back of Porous Si," Appl. Phys. Lett., Vol. 64, 2108, 1994.
13. M. Haond, O. Le Neel, "Lateral Isolation in SOI CMOS Technology," Solid State Technology, Vol. 34, No.7, pp. 47-52, 1991.
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Avid Kamgar received her PhD in physics from the University of Maryland. Since 1979, she has been a member of technical staff at Bell-Labs, Lucent Technologies, Murray Hill, NJ 07974; ph 908/582-3924, fax 908/582-5980, e-mail, [email protected].

James T. Clemens received his PhD in physics from the Polytechnic Institute of New York. He heads the VLSI research department at Bell-Labs, Lucent Technologies.

Types of isolation for standard CMOS VLSI

Types of isolation.Click here to enlarge image

• Within individual MOS devices, typical intra-device isolations (Fig. a) are a gate dielectric, which is an insulator, yet its role is to regulate the channel carrier density between the source and the drain by capacitance coupling; and junction isolation where isolation is created by applying a reverse bias voltage on the p-n junctions that create the source and drain structure.
• Inter-device isolation (Fig. b) is normally re-ferred to as lateral isolation; the field oxide suppresses spur ious surface leakage effects be tween active electrical components.
• Metal interconnect isolation (Fig. c) implies that no current should flow between metal lines connecting active devices, but parasitic capacitance coupling must be addressed.
• Intra-tub isolation (Fig. d) is the deleterious coupling of active devices through the silicon substrate within a tub.
• Inter-tub isolation (Fig. e) is the coupling be tween sub-circuit blocks fabricated on the same substrate but in different tubs. It can give rise to noise in more sensitive circuit components.

Avid Kamgar, James T. Clemens, Bell-Labs, Lucent Technologies Inc., Murray Hill, New Jersey