Technology News
IITC'99: Many options, many risks
08/01/1999
A fog of confusion - caused by too many options - continues to enshroud the future of on-chip interconnects, as attendees learned at the second annual International Interconnect Technology Conference (IITC), held in late May outside San Francisco. Low-risk evolutionary paths are desired, as fabs look to move beyond Al(Cu)/W/SiO2 structures. As a rule, almost all fabs will change only one major component (for example, the metal or the insulator) at a time.
While there has been a reduction in the number of different unit processes being considered for dielectrics, the number of potentially viable integrated process flows continues to increase. Companies will choose between many different paths, based upon each fab's device type (high performance vs. low cost, logic vs. memory, commodity vs. custom) and cumulative level of experience with the different unit processes that could be used in a complete flow.
One example of an innovative process flow and resulting interconnect architecture was presented by Kajita, et al. from Toshiba's ULSI Process Engineering Lab. The process involves combined damascene Cu lines, subtractive Al(Cu) vias (termed "pillars"), W/WN barriers (simultaneously Cu diffusion barriers and Al etch-stops), HDP-CVD of fluorinated silicate glass (FSG with k~3.3), and CMP of the FSG. The resulting structure demonstrated 20% lower line resistance and 30% lower via resistance than that of conventional dual-damascene Cu structures, at least in part because there is no via-etch to leave residues. Though the Al pillars are 0.2µm in diameter and 0.7µm high, the company claims they are robust enough to withstand the centrifugal forces of a spin-on dielectric process tool.
Though copper with low-k dielectrics continues to represent the ultimate near-term goal (since superconductors, optical interconnects, and air-bridges remain chimerical), the path is rife with pitfalls and hidden obstacles.
Many of these obstacles involve the integration of thin-film barrier layers, both metals and dielectrics. Applied Materials unveiled a new dielectric barrier (termed BLOk) that is deposited in a PECVD tool using Dow Corning organosilicon gas; with an effective k~5, the film offers a clear advantage over k~7 nitride in lowering the k of the entire stack. Many companies presented new results of work with metal barriers (including TiN, TaN, WN, and TaSiN), though all materials have advantages and disadvantages that make immediate selection difficult.
With a limit to the ability to scale interconnects and reduce overall wiring length, it is becoming clear that either chip size or the number of interconnect levels will have to increase. Either of these changes will reduce final chip yield, and Bell Labs researchers (Ruichen Liu, et al.) quantified the relative anticipated decreases. In order to achieve 2 GHz chips with Cu and low-k, "fat" top wires of 2-4x minimum dimension will be required. However, fat wires will increase chip size by 27-34%, with a possible corresponding decrease in yield. Though mandating complete redesign, a reduction in the cumulative wiring length is the only option that doesn't substantially increase manufacturing cost.
William Dally (Stanford University Computer Systems Lab.) discussed the theoretical limit to the advantages gained by hierarchical wiring. This approach involves three fundamentally different hierarchical levels to optimize bandwidth: local, with embedded registers for data and instruction storage; intermediate, with embedded registers for routing; and global, with switchable routers.
Dally advocates routing global signals through common wires instead of arranging wires (each dedicated to one signal) to get around wiring limitations. By replacing passive repeaters with switchable routers in an efficient design, up to a 10x improvement in on-chip bandwidth can be achieved with a simultaneous 10x reduction in the required wiring area. - Ed Korczynski