Future scaling must address within-device gate oxide variation
08/01/1999
 TEM data showing tox variations attributed to crystal orientation, surface faceting, and stress. (Source: Bell Labs, Lucent Technologies) |
A group of Bell Labs engineers at Lucent Technologies has data to show severe, random variation of oxide thickness (tox) within individual devices with sub-3nm gate oxide. They have determined this is due to different surface orientations and stress conditions as well as polysilicon intrusion from gate electrodes.
Reporting at the 1999 Symposium of VLSI Technology in Kyoto, Japan, C.T. Liu, a member of the Bells Labs technical staff, says, "This will become one of the limitations and challenges of gate-oxide scaling and qualification. It also demands further improvement of the shallow-trench isolation (STI) structures."
Specifically, the group found a 1.8 to 4.2nm physical range across the channel on devices with 2.5nm tox at the center of the channel. This was caused by different oxide growth rates determined by crystalline orientation and stress conditions in the local silicon surface, especially at the rounded corners of the STI. In addition, polysilicon intrusion from the gate electrode also causes local tox thinning.
 TEM data showing tox variations attributed to crystal orientation, surface faceting, and stress. (Source: Bell Labs, Lucent Technologies) |
The existence of these tox variations was first detected as multiple I-V "kinks," prompting the group to analyze the gate oxide with high-resolution transmission electron microscopy. They found five types of tox variation:
- From the channel center to the channel corner, the silicon surface crystal orientation changes from <100> to <111>, resulting in gradual increase of tox from 2.5nm to 4.2nm (see illustration). "This is a factor of 1.68, consistent with the expected difference of the linear growth rates on the two surfaces," says Liu.
- Rounding of the silicon surface from <100> to <111>, from the faceting of the top silicon atomic layers, results in local thinning and thickening of tox. The thinnest tox was 1.8nm (see a in illustration)
- Intrusion of polysilicon grains from the gate electrode into the thin gate oxide results in a local thinning of tox (see b in illustration).
- Tox thinning occurs at STI boundaries, as dramatically at 4.2nm to 2nm within a distance of <10nm (see c in illustration).
- A gradual tox variation at the center of the channel was probably caused by microscopic silicon surface faceting on the same <100> surface.
The dilemma for the industry is that, so far, corner rounding of the silicon surface at the isolation edge by means of local oxidation seems to be the most economic solution for eliminating the leakage. Liu says, however, "For the variation revealed in this experimental work, saturation current at 1.8V is degraded by at least 10%. Further, when either a constant field of 6.5 MV/cm or a constant voltage of 2V is applied on the gate electrode, the current density through the gate oxide increases many orders of magnitude from the 2.5nm area to the 1.8nm areas." This means that the outcome of any reliability measurements does not represent the property of the 2.5nm oxide. In situations like plasma damage, the antenna ratio to the critical areas becomes difficult to define as it may be device dependent.
Liu said his presentation to more than 300 of the symposium attendees "caught a lot of attention and many questions and discussions after the presentation." As for continued work at Bell Labs, however, he would only say, "research is ongoing."