Salicides and alternative technologies: Part 2

08/01/1999

Part 1 (Solid State Technology, June 1999) discussed evolutionary advances of Ti salicide processing, and the current best-practices for Co salicide formation. These technologies, currently ramping into production, will eventually fail to meet device requirements, as minimum device geometries continue to scale down. Beyond 0.1µm, low sheet resistance requirements combined with ultrashallow junctions may create incompatibilities with salicide processes, requiring alternative approaches to replace some or all of the functions provided by current salicides.

Epitaxial Co silicide

In addition to the reaction mechanism discussed in the Co salicide section (Part 1), it is possible for CoSi₂ to nucleate and grow epitaxially on (100) Si. A potential advantage of epitaxial Co silicide films is the achievement of smooth silicide-Si interfaces that could result in a better margin for diode leakage on ultrashallow junctions. Thin epitaxial silicides provide a shallow junction contacting technology that may open a path for further scaling of junction depths. However, a higher stress associated with the epitaxial layers [29] may be deleterious.

While epitaxial CoSi₂ can be grown under UHV conditions by molecular beam epitaxy (MBE), as well as by ion beam or pulsed laser synthesis, these techniques are either incompatible or impractical for salicide applications. Techniques were developed that achieve epitaxial CoSi₂ growth on (100) Si in a way that is compatible with salicide processing for industrial applications.

Figure 1. Shallow junctions obtained using Co salicide as diffusion source (SADS) process. Click here to enlarge image

One such technique consists of the deposition of a thin Ti layer (~5nm) before deposition of the Co film [16]. Alternatively, an ultrathin oxide layer (~0.5nm, which can be grown in a peroxide bath) produces a similar effect [17]. In both cases, the mechanism appears to be solid state epitaxy through a transport medium, with the main role of the interlayer being that of a diffusion barrier retarding the Co/Si reaction.

Several issues associated with the Ti interlayer process described, such as void formation at the silicide edges in patterned structures, significantly limit its applicability to salicide processing. The ability to control characteristics of an ultrathin oxide layer may also limit the application of this process in a production environment. Epitaxial CoSi₂ growth was also reported for a process in which a Co-Ti (10-20 at. %) alloy target was used [18].

Silicide as diffusion source

In the Silicide as Diffusion Source (SADS) process [30, 31], the conventional S/D implant and activation steps are skipped while a Co salicide is formed, followed by S/D dopant implantation into the silicide layer. A relatively low temperature anneal then drives the dopants from the silicide film into the underlying Si to form shallow junctions. Since dopants diffuse fast in the silicide film, an ideal junction is expected to follow the silicide/silicon interface contour (conforming to any existing interface roughness), allowing low diode leakage on the silicided ultrashallow junctions. Another benefit from SADS is low source-drain series resistance, due to high dopant concentrations at the silicide-Si interface and SADS compatibility with thin sidewall spacers.

Shallow junctions, with depths (X_j) of 40nm below the CoSi₂/Si interface at a concentration of ~1x10¹⁸cm^-3, were obtained by SADS processes using As implantation and low-temperature RTP (Fig. 1) [31]. Junction depths were observed to increase, as expected, as temperatures increased in the low temperature range. As temperatures increased to approach the baseline used in the conventional process flow (S/D implant and activation before salicide), SADS junctions became shallower due to As evaporation [31]. SADS junction depths are limited by this effect, as well as by the limited thermal stability of silicide films. A capping layer would aid in preventing evaporation at higher temperatures, allowing the formation of deeper junctions. Alternatively, other dopant species can be used instead of As.

Improvements in short channel characteristics for thin (35-55nm) spacers were verified for the SADS process in comparison with the conventional process, as better DIBL [V_t^lin(Vd = 0.1V)-V_t^sat (Vd = 1.5V)] were achieved [31].

Figure 2. Raised source-drain.Click here to enlarge image

One of the major concerns associated with silicided shallow junctions is diode leakage. Good diode leakage characteristics have been demonstrated with CoSi₂ as the diffusion source for both n⁺/p and p⁺/n junctions; however, most of the demonstrations were done in devices with low n-well and p-well concentrations that are not suitable for deep submicron CMOS applications. For a higher background concentration, the depletion region of a n⁺/p junction extends closer to the CoSi₂/n⁺-Si interface. If the junction is too shallow, the depletion region can extend through the whole n⁺ Si layer, and the shallow n⁺/p junction behaves as a Shannon contact with high diode leakage. Applicability of SADS is thus limited by the ability to obtain appropriate junction depths needed to achieve low diode leakage, given the background concentrations used in specific technologies.

Ni silicide

Ni silicides have been studied extensively [6-8], due to the low resistivity of NiSi (~15-18 µΩ-cm). A single RTP step at temperatures in the 400-500°C range forms the NiSi film. In contrast to conventional TiSi₂, the sheet resistance of NiSi is not affected by strong linewidth effects. A slight decrease in sheet resistance with decreasing linewidth can be attributed to thickening of NiSi films at gate edges [6]. A potential advantage of NiSi over CoSi₂ is that for the same silicide thickness, Si consumption for NiSi is only 80% of that for CoSi₂.

Figure 3. Raised source-drain structures increase the margin forlow diode leakage on shallow junctions.Click here to enlarge image

However, there are several difficulties for implementation of NiSi. Like CoSi₂, NiSi is sensitive to contamination that can lead to rough interfaces and higher diode leakage on shallow junctions. TiN capping layers and nitrogen doping can prevent oxidation from the ambient during formation, improving diode leakage [7]. High diode leakage on S/D-STI edge-intensive structures is a problem, correlated to film thickening and nonuniformity at these edges [8]. In addition, transformation into the high resistivity NiSi₂ phase needs to be prevented during later processing steps. NiSi films have poor thermal stability, with an increase in sheet resistance observed at temperatures as low as 600°C.

Raised source-drain structures

Raised source-drain structures [19-21] alleviate the stringent constraints on salicide processes that result from junction depth scaling combined with low sheet resistance requirements. An Si layer is selectively grown on gates (deposition can be optionally blocked from gates) and S/D areas (selective epitaxial growth) by CVD using a SiH₂Cl₂/HCl chemistry with H₂ as the carrier gas.

Since Si is consumed from the epitaxial layer, thicker silicide films can be grown on S/D areas without increasing diode leakage, making low-sheet-resistance silicide films compatible with shallower junctions. Raised source-drain structures were implemented into CMOS flows (Fig. 2), obtaining epitaxial Si that is facet-free at the sidewall spacer edge, and T-shaped gates down to 0.05µm in length [20]. Due to the T-shape of the gates formed by lateral Si overgrowth, a reverse linewidth effect for effective sheet resistance (computed using the physical length at base of gate) was observed both for Ti salicide with PAI and for Co salicide; sheet resistance values were 1-2 Ω/sq on 0.1µm gates [20]. Significant improvement in diode leakage was also observed for the raised source-drain structures in comparison with a conventional Co salicide process (Fig. 3) [20].

Figure 4. Process conditions are optimized to avoid faceting (left), obtaining facet-free growth (right).Click here to enlarge image

Several issues need to be ad dressed for the implementation of raised S/D processes [21]. Facet formation at the epitaxial Si-STI or sidewall spacer edges (Fig. 4), as well as macro and micro loading effects, need to be avoided by process optimization. Key issues for manufacturability include loss of selectivity (with nucleation on insulators a potential yield-limiting factor) and metrology for process control (due to the difficulty of measuring the epitaxial Si layer thickness, particuarly when deposition is blocked on polysilicon gates). Process conditions need to be optimized simultaneously for faceting, selectivity, and loading effects.

Selective Ti silicide deposition

One proposed replacement for conventional salicide processes is the selective deposition of silicide films on gates and source/drain areas [32]. CVD processes that selectively deposit TiSi₂ using TiCl₄, SiH₂Cl₂ (and/or SiH₄) with H₂ as carrier gas have been reported [32]. Key advantages are a significant reduction in the number of process steps, and less Si consumption for the same silicide thickness; when combined with selective Si epitaxy, selective TiSi₂ relaxes the constraints imposed by shallow junctions on contacting technologies.

In addition, lower silicide to source/drain contact resistance values are obtained when compared to conventional Ti salicide flows, leading to lower source and drain series resistance and higher drive currents. Excellent selectivity can be obtained, so implementation issues are more related to ensuring proper nucleation on the Si areas, particularly on surfaces with high dopant concentrations (rather than on avoiding nucleation on spacer and isolation, and bridging issues). The technique was demonstrated with a 0.25µm CMOS flow [32].

However, several issues remain that prevent the application of selective TiSi₂ processes to deep-submicron CMOS technologies. Surface preparation and control are critical to ensuring proper and uniform nucleation. Loading effects result in a dependence of both deposition rate and film thickness on the ratio of exposed-Si to isolation-area. Process conditions may be adjusted, or, alternatively, dummy structures may be incorporated in reticles to compensate for these effects.

Figure 5. W/TiN metal gate, Lgate ~60nm.Click here to enlarge image

The process is very sensitive to dopant concentrations at the Si surface - particularly As - which affect nucleation and growth characteristics. Selective deposition of undoped epitaxial Si layers, which are consumed in the subsequent selective TiSi₂ CVD deposition, have been used to address this problem. Unfortunately, this technique is still limited by the narrow line effects associated with the C49-to-C54 transformation and with agglomeration, so that higher sheet resistance or outliers at narrow linewidths may occur.

Poly-metal and metal gates

Some applications, such as DRAM and RF power amplifiers, may require very low gate sheet resistance. In combination with limits on acceptable layer thicknesses for scaled technologies, this may determine the need for metals with lower resistivity than silicides. A metal studied extensively for applications in gate electrodes is W, both in W-poly Si gates (using a diffusion barrier such as TiN), and in W/TiN metal gates (i.e., eliminating the poly-Si layer) [22, 23]. The latter approach eliminates the poly depletion concern, critical for sub-0.1µm CMOS.

By using a W/TiN gate stack, low gate sheet resistance of ~2 Ω/sq, independent of gate length down to ~0.05µm, was achieved (Fig. 5) [23]. Here, TiN provides good diffusion barrier properties between W and gate oxide, as well as a Si mid-gap workfunction. There are, however, disadvantages in using metal gates with workfunction close to the Si mid-gap for high performance sub-0.1µm CMOS. Studies conducted by TCAD device simulations [33] show the mid-gap workfunction results in a Vt that is often too high for conventional CMOS structures for high-performance applications, leading to degradation of both drive currents and short channel characteristics.

Flow modifications, CMP approaches,
and replacement gates

Alternative process flows can modify conventional structures to alleviate the scaling constraints for sub-0.1µm CMOS. These flow modifications can be aimed at increasing the amount of silicon available for silicidation in the S/D areas, producing various types of raised S/D structures, or S/D structures extending over isolation.

Another set of approaches decouples the processes that produce the S/D contacting silicide layer from those that produce the low-resistivity layers on gates, so that very low sheet resistance can be obtained on gates while maintaining low diode leakage on shallow junctions. A simple example is a flow in which a thin silicide is grown by a conventional salicide process; CMP is then used after pre-metal dielectric deposition to expose the top of the gates, allowing for a second salicide process used to grow thicker silicide films on gates. In contrast with conventional polycide processes, in which silicide films are grown on the poly Si before gate pattern and etch, salicide films grown on gates after dielectric CMP are not exposed to the high temperatures used in S/D activation anneals. Thermal stability of the silicide films is not a concern for the CMP-based flow, extending the application of polycide processes to very low sheet resistance scaled technologies. This flow adds process steps and complexity, however.

Figure 6. W/TiN replacement gate MOSFET, Lgate= 80nm.Click here to enlarge image

Alternatively, after exposing the top of the gates by CMP, a replacement gate process can be used to substitute metal for the original poly-Si gates (Fig. 6) [22]. After exposing the tops of the gates, poly Si and sacrificial gate oxide are etched. A gate dielectric is then grown, followed by deposition of a metal gate stack such as W/TiN or Al/TiN. Finally, a patterning step can be used to define T-shaped gates. Gate sheet resistance values of 1.5 and 0.35 Ω/sq were achieved using the replacement gate process for W/TiN and Al/TiN stacks, respectively [22]. The main advantage of this process is that the replacement gates are formed after all high-temperature steps are complete (such as those needed to build S/D and S/D extensions, which are incompatible with some metal gate and dielectric materials), so that more optimal, though thermally sensitive, gate dielectric and gate electrode materials may be used (leading to improvements in gate dielectric reliability and gate resistance). Additionally, certain high dielectric constant gate materials (such as Ta₂O₅) can be made ultrathin by eliminating interfacial oxides.

Conclusion

Ti and Co salicide processes suitable for implementation into sub-0.25µm technologies were developed at Texas Instruments with demonstrated manufacturability and high functional yield. Advanced processes for extension of Ti and Co salicide toward 0.1µm CMOS technologies, with low sheet resistance, low diode leakage, and high drive currents, were presented. Further scaling of junction depths combined with low sheet resistance requirements limits further extension of salicide processes into deca-nano technologies. Approaches to extend or replace the salicide flows and functions for deca-nano applications were reviewed.

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For more information, contact Jorge A. Kittl, Silicon Technology Development, Texas Instruments Inc., P.O. Box 650311, MS 3701, Dallas, TX 75265, e-mail:[email protected].