CMP processing with low-k dielectrics
07/01/1999
New low-k dielectric materials will change the CMP requirements for complete interconnect formation. Even for process flows that bury low-k materials under conventional oxide, integration challenges will remain due to changes in the physical properties of the new materials. Some CMP process variables - for both subtractive metal and damascene flows - will have to change radically to match the changes in materials.
The materials used to form ICs have remained rather constant at the same time that designs have shrunk and manufacturing methods have matured. On-chip interconnects, etched Al lines, W plugs, and silicon oxide insulators have become standard for virtually all high-volume technologies below 0.5µm. To realize such design rules, chemical mechanical planarization (CMP) of both interlevel dielectric (ILD) and W have become interconnect necessities.
CMP is still establishing itself as a mature manufacturing technology. The most commercially important CMP processes continue to be ILD, W damascene, pre-metal dielectric (PMD), and shallow trench isolation (STI). Despite the emerging trend toward new chip materials in advanced devices, not much change is anticipated for the PMD and STI processes. For processes that follow PMD, however, W-plug CMP will gradually be replaced by Al or Cu damascene line CMP, and ILD CMP may eventually disappear in an all-damascene world.
Low-k dielectrics are a wild card in the CMP deck. In one published CMP industry analysis [1], the market for low-k slurries is negligible through 2000 and amounts to only 0.15% of the CMP market activity by 2003. This does not mean that low-k dielectrics themselves will be so sparsely used; their market is projected to grow to $750M by 2003 [2]. Rather, the underlying process assumptions predict very little direct polishing of low-k materials. The market mainstream will rely on metal polishing for damascene architectures, and conventional oxide polishing of cap layers over low-k dielectrics for subtractive Al architectures. O`Mara & Associates [3] acknowledges the direct low-k CMP applications market only in passing, with no market outlook.
Predicting the ramifications of low-k dielectrics for CMP is truly a chicken-and-egg conundrum. Process and consumables requirements may vary widely, depending on the specific low-k material chosen. There is no volume manufacturing experience in the literature from which to draw. The CMP requirements will be a function of both the interconnect materials and the process architectures.
Shared concerns
Many of the CMP issues accompanying the introduction of low-k dielectrics are common to both subtractive Al and damascene approaches. Film adhesion is fundamental to all on-chip materials, particularly during CMP with high friction and shear forces at work. Most architecture proposals include capping the low-k dielectric with a traditional layer of silicon oxide or, in some cases, silicon nitride. The low-k materials must adhere well to both the cap layer on top and the substrate layer below, which is also likely to be a silicon oxide or nitride dielectric. "The moieties that reduce dielectric constant tie up the same chemical bonds that would otherwise be used for intermaterial adhesion," says Ken Monnig, director of advanced interconnects at Sematech. "We are currently developing modified edge liftoff tests to measure bond energies between films in order to quantify what ad-hesion strength is needed."
The compressibility of low-k films will make it possible for CMP processes to cause some local flexing within the interconnect stack. Such flexing could lead to cracking of the more rigid cap layers and localized delamination. In addition to unplanned exposure of the low-k film to slurry and post-clean chemicals, the lost cap fragments could lead to scratching. Consequently, polishing of cap layers on low-k is one of the earliest tests performed before a new low-k material can be considered integration-worthy. Though current evaluations are typically limited to simple one- or two-layer structures, stacks composed of 10 layers of FLARE or HOSP (low-k materials from AlliedSignal) with alternating SiO2 caps have shown excellent adhesion through 400iC thermal cycles.
Mechanical strength is particularly important for porous dielectric materials. The network of material encapsulating the pores must be strong enough to resist collapsing under the down force and unzipping under the shear force during CMP. Some early integration studies of porous dielectrics [4, 5] indicate that these films are able to withstand CMP abuse, especially with the added support of capping layers. "The mechanical stability of any buried low-k dielectric stack will need to be comparable to today`s SiO2 films. Anything less jeopardizes the reliability of the low-k structure," says Chris Yu, metal CMP program manager at Cabot. "But it`s the cap layer itself that is most relevant to CMP."
Most of the architecture options for incorporating low-k dielectrics keep the low-k material encapsulated, never exposing it to the CMP process and post-CMP clean. In these cases, the investments in processes, materials, and equipment for SiO2-based systems will carry over and maintain their value. Architectures that expose the low-k films to CMP will require special attention to defects, erosion, contamination, cleaning efficiency, and chemical compatibility. Post-CMP cleaning chemicals may require extra caution. We have found that ammonium hydroxide cleaning solutions can contribute to delamination of a SiO2 cap layer even when the underlying low-k material is not directly exposed.
Both metal dishing in large features and dielectric erosion in dense pattern areas are challenges for successful damascene planarization. As previously stated, some low-k materials, particularly fluorinated silicate glasses such as HDP-FSG [6], will be intolerant to exposure to CMP slurry or post-clean chemicals. Dielectric erosion must be less than the thickness of the cap layer (even in the most dense feature areas) to prevent low-k exposure (Fig. 1). Even if the low-k material is robust enough to withstand partial cap removal, the different remaining surfaces may tend to induce device performance anomalies that reduce final chip yield.
In addition to such gross problems, the mechanical properties of low-k stacks may give rise to more subtle effects. Both ILD and metal damascene CMP have been optimized for a rigid compliance between the interconnect stack and the polishing pad, with negligible compressibility within the chip. An increase in compressibility of the dielectric could make it more difficult to remove residual metal pools in low-lying areas. Metal pools could be the result of dishing in large metal features in a buried layer below; such dishing could be reduced through the use of higher polishing speeds or harder pads (including fixed-abrasive pads). "Another solution if the problem does arise is to use a nonselective slurry in a second process step," asserts Paul Feeney, dielectric CMP program manager at Cabot. "The cap thickness is critical, because it becomes a sacrificial layer, at least in part."
Yet another low-k problem during CMP is low thermal conductivity compared to SiO2. "Frictional heating in the CMP process may give rise to hot spots, possibly resulting in localized stress and cap delamination," states Kevin Witt, copper program manager at Rodel. "We need to fingerprint the thermal characteristics of polishing better." High-linear-speed equipment being developed for greater planarization efficiencies would exacerbate this problem. In the extreme, local temperature excursions may further cure the low-k film, resulting in nonuniform dielectric properties.
Defect detection in low-k dielectrics does not yet seem to pose any new challenges unique to CMP. "The wavelengths currently used for optical thin-film metrology work for low-k materials as well," says Anantha Sethuraman, senior director of CMP solutions for KLA-Tencor. "Detection of embedded particles in low-k materials represents one new challenge." Direct polishing on low-k dielectrics is likely to result in new defect classifications [7] as illustrated in Figure 2.
Limited R&D resources and more immediate priorities continue to slow work on low-k CMP. "The level of CMP experience among the low-k dielectric segment of the process development population may be lower than you`d like," observes Willy Krusell, VP of the CMP Division at Lam Research. "The experienced CMP talent pool is still heavily focused on tungsten- and ILD-manufacturing implementation, followed by copper CMP development." Most experienced CMP professionals are currently working on ramping volume production at fabs worldwide. "If anyone is seriously working on CMP specifically for copper with low-k, they`re not talking," says Cabot`s Feeney. "We`re in the secrecy tunnel."
Subtractive Al with W-plugs
The insertion of low-k dielectrics into subtractive Al/W interconnects arguably represents the lowest-cost method for introducing new dielectric materials. However, the resulting enhancement of device performance may be insufficient to justify the cost of implementation. Regardless, it can safely be assumed that some segment of the fab population will move down this path.
The CMP challenges of this architecture revolve around the cap layer that will presumably be used over the low-k dielectric (Fig. 3). The primary variable is the height at which the low-k material ends and the SiO2 cap layer begins relative to the height of the etched Al line. In cases where SiO2 comprises the entire via-level dielectric, both W and ILD CMP processes should not essentially change.
The planarity of the capped low-k stack prior to ILD CMP subtly alters the CMP requirements for this architecture. As the surface becomes planar, more and more bulk material needs to be removed in order to further increase the degree of planarization. The planarity of the as-deposited dielectric stack is a complex function of the thickness of each material relative to the line thickness, the deposition methods of each, and whether or not a low-k etchback occurs prior to cap deposition. The as-deposited planarization of spin-on materials in dense pattern areas can approach that of standard ILD CMP (Fig. 4), rendering further planarization by CMP highly inefficient. One solution is to deposit a thicker cap oxide and polish longer, but this decreases throughput for both CVD and CMP.
A preferred solution involves more efficient planarization processes, which can be achieved by higher linear speeds, fixed abrasive polishing pads, or (possibly) tailored CMP slurries with modified particles and chemistry. "This is where fixed abrasive technology will pay off," says John Givens, CMP section manager at VLSI Technology in San Antonio, TX. "Bulk removal rate is not the driving issue; planar distance and planarization efficiency are."
Another option is to design the process so that the oxide cap is completely sacrificial (deposited over the low-k to reduce environmental sensitivity to process delays prior to the next step). An oxide cap would provide a known adhesion surface for W deposition, even if the metal is in direct contact with the low-k on via side walls. The W CMP process would be expected to remove the entire oxide cap. A further variant eliminates the cap deposition entirely, depositing the W and liner directly on the low-k. In either case, the need for a defect-free, low-k surface
following CMP would place new requirements on the consumables and equipment sets; it is likely that the post-CMP cleaning process would have to be modified.
Dual-damascene: Cu
The most common word association for "low-k" is "copper." ILD CMP is eliminated (though some variation may be needed for buffing) in dual-damascene Cu processing. As long as barrier metal deposition remains compatible with the high aspect ratios of dual-damascene trenches and vias, there is little motivation to develop single-level Cu damascene (requiring a greater number of unit process steps, resulting in higher costs and lower yields). Only when the sputtering limits are approached will the market bifurcate to CVD-barrier metals with dual-damascene or sputtered barriers with single-level damascene.
Barrier metal changes are significant to CMP because the polishing of Cu is easy, but the polishing of barrier metals is extraordinarily challenging. As a fast diffuser through SiO2 and many other dielectrics, Cu requires a very dense diffusion barrier. The aggressive chemistry needed to remove tantalum and tantalum nitride can passively etch the remaining Cu, requiring creativity in slurry formulation. There is currently much debate as to the relative merits of removing the surface Cu and the barrier tantalum in one step vs. two steps (allowing separately optimized slurries).
The most commonly published dual-damascene structures have a hard mask between the via and line dielectric layers, and another hard mask on top of the line dielectric (Fig. 5). This top hard mask is typically SiO2, since its dielectric constant is significantly lower than that of SiNx. (The effective dielectric constant of the stack is a composite of all of the layers). The SiO2 hard mask remains in place during metal deposition, so it can later serve as a polish stop for Cu CMP. Since this results in the same materials system (Cu/TaN/SiO2), the developed consumables, equipment, and processes for Cu on plain SiO2 should be extendible to Cu on SiO2-capped low-k.
CMP dishing and erosion are more problematic for Cu (line-level with buried plugs) than for W (plug formation only), because of the dramatic differences in the conductive run lengths of these two feature types. The thinning of Cu lines by CMP can give rise to unacceptable variations in line resistance [8] and device performance, while the electrical ramifications of dishing and erosion in W CMP are relatively small.
The requirements for Cu dishing with low-k are not likely to change significantly from the requirements with SiO2 dielectric. However, it is likely that the allowable dielectric erosion will dramatically decrease. In dense pattern areas, the loss of Cu line thickness is more likely due to wide area decreases in dielectric stack thickness, rather than the loss of Cu within individual lines. The oxide cap over the low k becomes a primary supporting structure against this metal loss by dielectric erosion. If the oxide cap were to break through and expose the low k below, the local erosion rate could change abruptly in either direction (depending on the Cu slurry and the specific low-k material). Though some low-k materials are removed very slowly in Cu CMP, it is likely that exposed low k will either erode faster, swell up, or both. To minimize oxide cap loss, the ability to stop more easily on the TaN barrier may motivate interest in two-step Cu CMP processes.
Inherent to the process conditions necessary for low cap erosion is an increased difficulty in removing scratches in the SiO2 cap. "We have seen replication of scratches through the CVD dielectric stack from one level to the next in copper damascene," says KLA`s Sethuraman. "The use of capped spin-on low-k layers will smooth this right out."
Since it is the effective dielectric constant of the entire stack that determines device performance, it is desirable to eliminate any SiO2 (k ~4) layers from the low-k (<3) stack. A silicon nitride (k ~7) barrier is typically required to isolate Cu before deposition of the next dielectric level, and a cap oxide combined with this nitride layer may raise the stack k to unacceptable levels (resulting in minimal benefit over standard oxide ILD). Elimination of the oxide cap will probably require a two-step Cu CMP process, with the second step determined by the selectivity to the low-k dielectric that would be the primary polish stop. Defectivity and cleaning efficiency of the exposed low-k surface are additional problems. Solutions will be constrained by the need to minimize further Cu losses due to dielectric erosion.
It is unlikely that many fabs will take the option of depositing a barrier metal and Cu directly on a low-k dielectric. Much research has been invested in studying the adhesion and effectiveness of Cu barriers on SiO2 (in part, because SiO2 films are easily obtained and have similar salient properties regardless of the source). The many different low-k materials have very different salient properties, and their properties with Cu barriers are still undetermined. This lack of barrier reliability data, combined with an extreme sensitivity to Cu as a fast diffuser, makes this a daring approach for the time being. The process implications for CMP collapse into those for the scenario in the preceding paragraph.
Damascene: Al lines & plugs
Low-k materials may also be incorporated into Al damascene flows. The differentiating characteristic between Cu CMP and Al CMP is that Cu forms soft oxides as it is oxidized and removed, whereas the Al oxidation pathway may proceed through Al2O3 (an abrasive used for metal polishing). While this hard oxide formation can be avoided once the removal process is underway, native oxide on Al may resist initiation of the polishing process and contribute to scratching.
Another differentiation for CMP between these two metals is that Al uses titanium barriers rather than tantalum. Over time, clever ways of dealing with titanium barriers have been developed for W CMP that may lend themselves to Al CMP. Issues of dishing and erosion carry the same weight and consequences for Al lines as they do for Cu lines. Depositing the titanium barrier and Al directly on low k (without a cap layer) is perhaps less risky than attempting direct Cu metallization on low k. While adhesion of titanium is uncharacterized, there is less concern over Al diffusion through the barrier.
The unique implications of Al damascene for CMP are less technical and more market related. "Normally you see copper damascene compared with subtractive aluminum, not aluminum damascene," explains VLSI`s Givens. "Aluminum damascene offers lower resistivity by using titanium barriers rather than tantalum. Aluminum diffusion is not as challenging an issue as Cu diffusion. It doesn`t require insertion of a nitride Cu barrier in the dielectric stack. If I could polish down to the low-k material, I wouldn`t use a dielectric cap at all. This kind of aluminum damascene structure could out-perform copper damascene." Some segment of the fab-user community will adopt this approach. If the customer base is not satisfied with what is available from the CMP suppliers, inventive Al etchback suppliers may evolve to exploit the market niche.
Summary
The ultimate picture of CMP in the era of low-k dielectrics will be a composite based on many higher-order a priori decisions. How far can you extend the present material set? With what architecture and materials can you achieve the highest performance gain for the lowest capital investment in the shortest time? How will the materials chosen dictate the process sequence? How will the process sequence dictate the CMP requirements? How will you deal with a barrier metal that is intended to be impenetrable? "You can count on four to five years of confusion while choices are made for the next combination of metals, dielectrics, and architecture," warns Tom Tucker, president of Laredo Technologies, a CMP consulting firm.
There are very few interconnect decision pathways that include CMP early in the chain, so very few critical decisions will be made because of CMP. Finding solutions to challenges that have been imposed by circumstances beyond your control tends to foster a creative environment, and we`ve come to expect the emergence of new inventions in the semiconductor-processing industry. The interplay between CMP and low-k dielectrics will mandate the deployment of many creative new solutions.
Acknowledgment
The author thanks colleagues from Sematech, chip fabs, and CMP equipment and consumable suppliers for hours of valuable and entertaining discussions; and Anna George, Jude Dunne, and the AlliedSignal Microelectronics & Technology Center for leadership in demonstrating the integration of low-k dielectrics for interconnects. FLARE and HOSP are trademarks of AlliedSignal.
References
- Kline & Co., "The Outlook for CMP Technol. & Materials, 1998-2003," pp.1-5, 1998.
- R. Castellano, Semiconductor Dielectrics Market, The Information Network, 1999.
- O`Mara & Assoc., "IC Planarization by CMP: A Worldwide Assessment of Technology and Markets Through the Year 2010," pp.4-41, 1998.
- C. Jin, "Porous Silica Xerogel for Interconnect Applications," Sematech Ultra-low-k Workshop Proceedings, pp. 323-346, 1999.
- E. Todd Ryan et al., "Unit Process Development and Integration Studies of Mesoporous Silica Using a Copper Damascene Architecture," Sematech Ultra-low-k Workshop Proceedings, pp. 347-366, 1999.
- H. M`Saad et al., "Integration of HDP-FSG as ILD Material in Multilevel Interconnect Devices," Proceedings of the Dielectrics for ULSI Multilevel Interconnect Conference (DUMIC), pp.210-219, 1999.
- M.A. Fury, D. Towery, "Chemical Mechanical Polishing of Polymer Films," Journal of Electronic Materials, Vol. 27, No.10, p. 1088, 1998.
- V. Blaschke et.al., "Integration Aspects for Damascene Copper Interconnect in low-k Dielectric," Intl. Interconnect Technology Conf. Proc., pp. 154-156, 1998.
Author
Michael A. Fury received his BS in chemistry from Iowa State University, and his PhD in physical chemistry from the University of Illinois, Urbana. He has held positions at Rodel, Rippey, and IBM. Fury is the director of process integration at AlliedSignal Inc., Advanced Microelectronic Materials, 1349 Moffett Park Dr., Sunnyvale, CA 94089-1134; ph 408/962-2017, fax 408/980-1430, e-mail [email protected].