Simplified interconnect processing for cost-sensitive chips

07/01/1999

A simplified process flow for the manu-facture of consumer-electronics logic ICs cuts the number of required interconnect processes by two-thirds. Local planarity is achieved by combining two-stage (low- and high-temperature) Al sputtering with flowable dielectric SiH₄ and H₂O₂ CVD, while global planarity is enhanced by dummy patterns. As a result, wafers do not require CMP. This strategic tech-nology provides significant savings in both cost and time-to-market.

A new technology has been developed specifically for the consumer-electronics logic IC market that slashes the number of multilayer metallization processes by two thirds, and reduces both manufacturing costs and time-to-market in roughly the same proportion. Manufacturing costs are improved by reductions in both capital equipment investments and running costs.

In-house trials imply that the new technology will also boost yield, thereby reducing overall effective cost even more. The yield increase is due to the elimination of processes that are sources of particle generation. This simplified approach is expected to make it possible to commercialize profitable consumer logic ICs.

The new technology will be implemented sequentially, starting from the top-layer Al metallization on logic ICs for consumer electronics. It is currently targeted at ASICs and microcontrollers. ASICs designed for use in low-priced consumer electronics will be manufactured at lower cost and will therefore find application in new markets previously difficult to enter.

Consumer electronics are extremely cost-sensitive, and there are cases where, for example, some customers may be willing to buy an ASIC for $0.90 but not for $0.91. Reducing the number of multilayer metallization processes by two thirds will drop the cost of low-end ASIC chips (with a small number of interconnect layers) by at most only 10%, but customers often select the lowest-priced chip. Further, while the unit price of this type of chip is low, the large manufacturing volume contributes to sales revenues.

For high-performance chips with five interconnect layers, metallization processes account for about half of total manufacturing process steps. Reducing the number of these metallization process steps by two thirds would significantly reduce overall chip cost.

Metallization

Multilayer interconnects have required more and more process steps to continue to meet chip performance demands, including tungsten (W) vias, chemical-mechanical planarization (CMP), multilayered dielectric films, and TiN barriers. Additional steps mandate increases in equipment investment and time-to-market. Moreover, because many of these processes can generate particles, they have often contributed to reduced yields.

To manufacture ICs with high quality and low cost, we analyzed all potential processes without limiting ourselves to currently accepted technologies. We then developed a simple and high-quality multilayer Al metallization technology consisting of four key elements (Figs. 1, 2):

• Ti barrier metal,
• Al sputtering to complete via filling and line formation in one process,
• self-planarizing interlayer dielectric deposition in one process, and
• multilayer layout design.

These constituent technologies allow for a reduction in the number of metal interconnect deposition processes from eight to two, and in the number of interlayer dielectric deposition processes from six to two. In metallization, barrier metal sputtering, W film growth, W etch-back, and associated clean and inspection processes are all eliminated. Al lines and vias can be handled in a single sputtering system, and Al vias reduce contact resistances by two thirds (compared to W). Interlayer dielectrics no longer require plasma tetraethylorthosilicate (TEOS) or CMP processes.

Ti barrier metal

We developed a more efficient barrier metal technology that removes conventional TiN reactive sputtering requirements. Conventional contact hole barrier metal is a TiN/Ti layered stack, formed by separate sputtering processes to ensure that W plugs meet stringent leakage current requirements. TiN reactive sputtering contributed to reduced yields because of particle generation.

The new process generates TiN through nitridation of the initial Ti film that is formed through sputtering. It was shown experimentally that this technique prevents Al penetration to the Si wafer.

Simultaneous Al line and via formation

Al sputtering technology to form lines and vias simultaneously in a single process eliminates the need for W vias. In developing processes to form the new Al vias, it was essential to prevent the generation of voids. This was accomplished by devising a sputtering technique providing complete control of Al reflow, thereby preventing discontinuous Al aggregation and oxidation inside vias.

This sputtering technology consists of (a) degassing at high temperature after via etch, (b) formation of a Ti barrier layer through collimated sputtering and nitridation, (c) wafer cooling, (d) high-speed, low-temperature Al sputtering (to suppress generation of Ti compounds by keeping wafer temperature low), and (e) low-speed, high-temperature Al sputtering in the same chamber as step (d). The reflow of the Al film grown at high temperature over the first deposited Al film at low temperature allows complete via fill.

To confirm that the process does not create voids in vias, a 0.25µm test IC was fabricated with three Al layers. Transmission electron microscope (TEM) cross-section photomicrographs were digitized and Fourier transformed to analyze the structure (Fig. 3). Results show complete Al plugs in vias. The Al vias are connected to the underlying Al interconnect through Al₃Ti compounds, resulting in low via resistance.

As well as voids, there are two main problems with the new metallization: fine whiskers (monocrystalline Al) and Al surface roughness. Whiskers are caused by tensile stress in the Al film, which is generated by a thermal expansion difference between the Al and the underlying SiO2 during high-temperature reflow. Whiskers about 0.2µm in diameter and 1µm in length (formed around vias) were particularly problematic because they caused pattern shorts. Al surface roughness had to be reduced to improve optical lithography alignment precision. Both problems were solved through control of sputtering temperatures and gas flow rates.

Self-planarizing dielectrics

To confirm 100% via fill, sufficient reliability, and both within-wafer and wafer-to-wafer uniformities, we fabricated a test element group (TEG) to measure via resistance, electromigration and stress migration reliability. Results show that the new Al metallization, when combined with conventional inorganic spin-on-glass (SOG) layered dielectric films, yielded unsatisfactory reliability and degraded interconnect life.

An investigation showed thinned portions in the Al vias where SOG was exposed. The cause was determined to be SOG outgassing, and thermal desorption spectroscopy (TDS) was used to analyze what gases were emitted by the wafer during high-temperature Al sputtering. Results show large volumes of OH and H2O emissions from 150 to 250iC, and H₂ above 300iC, large enough to degrade the deposition pressure. The same test was performed for other interlayer dielectrics, showing the largest emissions of H₂, H₂O and CO₂.

To overcome these problems, we developed a new interlayer dielectric technology to replace SOG. The new interlayer dielectric film growth technology is capable of interconnect gap-fill and planarization in a single process. The new technology solves reliability problems caused by the integration of the new Al sputtering technology with existing interlayer dielectrics. The number of process steps required was reduced while eliminating the final complexity of conventional multilayered dielectric films.

This technology makes use of the silanol reaction, whereby silane and hydrogen peroxide react at 0iC on the wafer surface to create silanol.

SiH₄ + 3H₂O₂ -> Si(OH)₄ + 2H₂O + H₂ (1)

Silanol has extremely low viscosity and self-planarizes, so that it can fill holes at 0.2µm intervals with flat upper surfaces. Silane can be converted into a stable SiO2 film through a condensation polymerization reaction in the same process tool, at 350iC under vacuum.

Si(OH)₄ -> SiO₂ + 2H₂O (2)

To assure good contact and planarization with the silanol dielectric process, an SiO₂-base film is essential. In addition, a porous plasma SiO₂ cap layer is needed to alleviate tensile stress in the film while removing H₂O from it during polymerization. All three layers can be formed in the same process equipment, while maintaining process pressure. An N₂ anneal at atmospheric pressure and 450iC creates the final uniform dielectric film.

Vias in this triple layer dielectric were easily filled with the new Al sputtering technology. TDS analysis of the triple layer dielectric revealed essentially no H₂O or H₂ outgassing from vias during heating to 500iC in vacuum (resulting in a minimum available pressure 10x lower than SOG). Analysis of impurities in this triple layer dielectric (after removal of H₂O by annealing) showed uniform levels of H, N, and F, with no harmful impurities generated. Electromigration tests of the new interconnect (combining the new dielectric with the new metal) showed that reliability targets were met.

Layout optimization

A new layout technology for multilayer interconnects was then developed to take full advantage of the technology described above. Dielectric height differences caused by varying Al line widths and spaces can be suppressed by forming appropriate Al dummy patterns (Fig. 4). A dummy pattern with a line interval of 1?m or more can suppress global height differences to within 150nm, and local height differences to within 220nm.

As wafer surface height differences can be held to these limits, CMP is no longer needed, and its elimination provides major reductions in the number of processes, overall cost, and time-to-market (Fig. 5). Though dummy patterns cannot produce the same degree of planarization as CMP, height differences can be brought within the optical lithography depth-of-focus.

Conclusion

If the simplified process flow is applied to the formation of a 0.25?m-rule, five-layer Al interconnect, it is possible to eliminate up to 50 process steps. The new approach is simple and efficient. For example, without W-CVD or W etch-back processes there is little fear of interlayer shorts even if the dielectrics are not perfectly flat (a rough dielectric causes W residue in etch-back, leading to shorts).

This new technology is different from that chosen by many IC manufacturers. The literature shows a large number of papers on Cu interconnect and low-k dielectric films. low-k dielectrics improve speed and reduce power dissipation of a chip, and we plan to incorporate low-k films into our dielectric technology as well. It is currently unclear whether Cu lowers interconnect resistance enough (due to the existence of high-resistance barriers and CMP dishing) to offset equipment investment; Cu is a target for future evaluation and development.

Ultimately, the goal is to enhance consumer product speed. Development must therefore be oriented toward chip-on-board (final mounted product form) speed improvements, not mere on-chip improvements (such as Cu and/or low-k). Stability of the newly developed technology is currently being evaluated for volume production, and plans exist for the initial introduction at the upper Al interconnect layers of logic ICs.

Acknowledgments

Project members include Naohiro Miriya, Yukio Morozumi, Kazumi Matsumoto, Fumiaki Ushiyama, Junichi Takeuchi, Masaharu Taniuchi, Mamoru Endo, Takanori Asahi, and Eiji Suzuki.

Text translated by Yosuke Mochizuki and Mitsuaki Nagahiro of Nikkei Microdevices. Translated text edited by Ed Korczynski, Senior Technical Editor, Solid State Technology.