Cobalt silicide processing in a susceptor-based LP-RTP system
07/01/1999
Woo Sik Yoo, Ashur J. Atanos, Jean-Francois Daviet, Mattson Technology Inc., Fremont, California
Very thin cobalt silicide formation and annealing were investigated using a susceptor-based low-pressure RTP system. Cobalt silicide process sensitivity was investigated as a function of process temperature (350~700?C), process time (60~120 sec), and Co film thickness. A production-worthy shallow silicide contact formation process has been developed with backside emissivity independence using the system. A wide process window and excellent sheet resistance uniformity have been demonstrated for cobalt silicide process integration steps. The net added nonuniformity of typical TiN capped 10nm-thick cobalt films was less than 0.5%.
The formation of reliable and low-resistance thin silicide contacts to Si is still a significant challenge for metal-oxide-semiconductor field effect transistors (MOSFETs) with <0.18?m design rule [1]. Of the low-bulk electrical resistivity silicides such as CoSi2, TiSi2 and NiSi, CoSi2 is particularly attractive for small-scale device applications because of its small grain size and ease of formation on narrow Si lines. CoSi2 with a resistivity of 16~18?Wcm has a comparable conductivity value to TiSi2 [2]. Cobalt silicide is processed at lower temperatures (350~700?C). In this temperature regime, typical lamp-heated rapid thermal processing (RTP) systems exhibit problems with temperature control, repeatability, and uniformity [3]. The huge emissivity change [4] observed in cobalt films during the thermal reaction process makes temperature control in lamp-heated RTP systems very difficult. Accurate and reliable wafer temperature measurement/control below 600?C using optical pyrometry is still a significant technical challenge in lamp-heated RTP systems. Alternative RTP techniques are being actively investigated by several groups to resolve these issues.
The feasibility and production-worthiness of a constant heat source, susceptor-based dual wafer RTP system were previously demonstrated with TiSi2 and CoSi2 [5-8]. This system has many advantages from the viewpoints of within-wafer and wafer-to-wafer temperature uniformity, throughput, and energy efficiency. It is extremely promising for low-temperature applications in which conventional lamp-heated systems show difficulties in getting consistent process results.
Using TiN capped cobalt films of three different thicknesses, we investigated very thin cobalt silicide formation and annealing using a susceptor-based, low-pressure RTP system (Aspen RTP). The effect of backside emissivity on sheet resistance (RS) and uniformity of cobalt silicide layers was also investigated using wafers with different backside film structures.
RTP process chamber
 FIGURE 1. Schematic diagram of susceptor-based low-pressure RTP system. |
The process chamber incorporates a massive, thermally stable, constant temperature heat source (a silicon-carbide-coated graphite susceptor) in a low-pressure chamber attached to a vacuum loadlock. A cross section of the process chamber is shown in Fig. 1. The wafers are placed in close proximity (<500?m) to the susceptor, which is heated from below using a specially designed resistive heating element. The desired distance between the wafer and the susceptor is controlled via SiC standoffs. The susceptor provides two process pockets for processing two 125mm, 150mm, or 200mm dia. wafers simultaneously.
The entire unit (susceptor and heater) is enclosed inside a thermal shield contained within a water-cooled aluminum vacuum chamber. The wafers are typically processed in the pressure range of 1~50torr. The thermal shield and vacuum provide excellent thermal insulation. Consequently, the wafer temperature uniformity (which is dictated by the susceptor and heater design) is independent of the process temperature. In this system`s process chamber, the temperature of the susceptor is controlled by an optical pyrometer to provide an identical thermal environment for all wafers regardless of wafer conditions. A nearly isothermal environment where the wafers are processed is created by the large mass susceptor, the thermal shield and vacuum. The susceptor temperature is also constantly monitored by an embedded thermocouple, acting as a pyrometer watchdog.
Wafer temperature during process
 FIGURE 2. Typical wafer temperature profile during processing. |
Figure 2 shows a typical wafer temperature profile during process at a susceptor temperature setpoint of 700?C and pressure at 2.0torr. Wafers are heated as soon as they are introduced into the preheated process chamber. Wafer temperature increases exponentially and approaches susceptor temperature with time. Wafers are quickly removed after processing at close to the process temperature and are then placed into an actively cooled cooling station. An exponential ramp down of the wafer temperature is also observed during cool down.
As chamber pressure is increased, both ramp rate and maximum wafer temperature increase due to the change in heat transfer characteristics of the gas media. Details of the wafer temperature profile and ramp rate will be reported elsewhere [9] as a function of susceptor temperature set point and pressure.
Experimental procedure
 FIGURE 3. Schematic cross section of TiN capped Co films on a Si wafe3r. |
To investigate very thin cobalt silicide formation and annealing processes, TiN (10nm thick) capped cobalt films (10nm thick) on 200mm Si wafers were mainly used. TiN capped 7nm and 13nm cobalt films were also used for thickness dependence of RS. A schematic cross section of these TiN capped Co films is shown in Fig. 3. Cobalt silicide process sensitivity was investigated as a function of process temperature (400~660?C), process time (60~120 sec), and Co film thickness. Process times cited in this paper refer to the wafer residence time (from wafer-in to wafer-out) in the heated process chamber. In contrast, the process time referred to in lamp-type RTP systems is the soak time at process temperature regardless of overhead times such as preheating and cool down times.
Sheet resistance of TiN capped Co films was measured using a four-point probe before and after annealing. Forty-nine points were measured to generate contour maps with 4mm exclusion from the sputtered film edge (8mm from the wafer edge).
In a series of process repeatability wafers, RS and uniformity change were tracked during the cobalt silicide process integration. The RS uniformity data was obtained on the as-received samples, after the first step anneal with TiN cap in place, after TiN removal by wet etch, and after the second step anneal. For the backside emissivity sensitivity test, three different backside film structures using SiO2 and polycrystalline Si were prepared.
Temperature sensitivity
 FIGURE 4. Sheet resistance (Rs) and net added nonuniformity(NANU) of TiN capped 10nm-thick cobalt films. |
Figure 4 shows the RS and net added nonuniformity (NANU) of TiN capped 10nm-thick cobalt films in the temperature range of 400~660?C. Process time and process pressure were 90 sec and 2.0torr, respectively. The N2 gas flow rate was kept at 2000sccm during the process. Average RS and uniformity of the received films were 20.5W/sq and 2.1%, respectively. As temperature increased from 400?C, the RS of the films started to increase due to the CoSi2 formation. For process temperatures between 460 and 560?C, the RS became constant at ~50W/sq. Then, at around 580?C, the RS rapidly decreased as temperature increased due to the phase transition. Above 600?C, the RS became constant again. Except for the phase transition regions around 420 and 580?C, the NANU remains negative (i.e., RS uniformity has improved after annealing). Because of the nearly isothermal environment in the process chamber, NANU remains below 10% (1s) even in the phase transition regions.
Two flat temperature regions on the temperature sensitivity curve (Fig. 4) can be considered as process windows for first step and second step CoSi2 annealing processes: 460~560°C, and >600°C, respectively. Very wide process windows for both first and second step CoSi2 anneal were characterized. In a production environment, a wide process window is desirable because it provides robust process results. To have a wide process window determined by the thermal reaction mechanism of a material, we must have good temperature controllability as well as good linearity between the nominal process temperature and real wafer temperature.
Time and film thickness sensitivity
Cobalt film thickness and process time dependence of RS were investigated at 500?C. Figure 5 shows the sheet resistance of TiN (10nm) capped Co films after annealing at 500?C as a function of Co film thickness and process time. Three types of Co film thicknesses (7nm, 10nm, and 13nm) were used in this study. Process time was varied from 60 sec to 120 sec. The thicker the Co film, the lower the RS. As seen in the figure, process time has a very small effect on the RS after the CoSi2 is formed.
 FIGURE 5. Sheet resistance (Rs) and NANU as a function of Co film thickness and process time (process temperature=500 C, process presure=2.0torrm, N2 flow=2000sccm). |
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Process repeatability
To test process repeatability, we performed a 500-wafer marathon run at the second step anneal condition (660?C, 90 sec). Thirty-two reacted cobalt silicide wafers were used in the test after TiN cap removal. To investigate the accumulation effect of air exposure after wet etching of the TiN cap layer, the wafers were placed in four different blocks (eight wafers in each block). The test started six hr after TiN cap removal, and there was a two-hr air exposure time difference between blocks. In other words, the eight cobalt silicide wafers in the second block have eight hr of air exposure before the second step anneal, 10 hr in the third block, and 12 hr in the last block. In addition, no accumulation effect of air exposure up to 12 hr after TiN cap removal was observed from this test.
Sheet resistance and uniformity changes were tracked at each step in the cobalt silicide process integration. We selected 500°C and 660°C as process temperatures for the first step and second step CoSi2 anneal, respectively. The RS and uniformity data were obtained on the as-received samples, after the first step anneal (500°C, 90 sec) with TiN cap in place, after TiN removal by wet etch, and after the second step anneal (660°C, 90 sec). Figure 6 shows the average RS and uniformity of eight samples after each of the process steps. The average RS changed from 20.50-51.24W/sq after the first step anneal. By removing TiN cap layers in wet etchant, the average RS became 89.30W/sq. A very low average RS of 5.73W/sq was obtained after the second step anneal. An excellent average RS uniformity of 1.18% was achieved after the final step (second step anneal) in cobalt silicide integration. The NANU throughout the process steps was -0.87% (i.e., the RS uniformity improved during the process steps).
 FIGURE 6. Average sheet resistance and uniformity of eight samples after each process step. |
Within-wafer temperature uniformity and wafer-to-wafer temperature repeatability of this susceptor-based, low-pressure RTP system were measured by optical pyrometer and confirmed by CoSi2 and TiSi2 process results. [5] The 1s values for both within-wafer temperature uniformity and wafer-to-wafer temperature repeatability were <1.0?C in the entire CoSi2 process temperature range of 400~660?C.
Backside emissivity sensitivity
The effect of backside emissivity on RS and uniformity of cobalt silicide layers was investigated using wafers with different backside film structures. SiO2 (100nm) and polycrystalline Si (50, 150, or 250nm) were deposited on both sides of silicon wafers using low-pressure chemical vapor deposition (LPCVD). TiN (10nm thick) capping layers and Co films (10nm thick) were sputtered on the front side of the polycrystalline Si-deposited wafer.
 FIGURE 7. Normalized temperature sensitivity curve for sheet resistance change ratio (post -Rs/pre-Rs) in TiN/Co films on various Si under layers |
Figure 7 shows the RS and the NANU of TiN capped Co films on Si (100) and polycrystalline Si with different backside film structures in the temperature range of 350~700?C. Since the average RS and uniformity of as-received TiN capped Co films were different between film structures, the RS change ratio (post-RS/pre-RS) was plotted as a function of temperature. The RS trends versus temperature for polycrystalline Si-deposited wafers were similar to TiN capped Co films on Si(100) wafers. As temperature increases from 350?C, the RS of the films starts to increase as various phases of cobalt silicide are formed. For process temperatures between 460?C and 520?C, the RS change ratio became constant at 3.0. The RS change ratio in Co/Si(100) is constant at 2.6 in this temperature region. The sheet resistance of Co/poly-Si varies between 74.4~85.4W/sq depending on the film structure. Then, at around 560?C, the RS change ratio and RS rapidly decrease with temperature increase due to the phase transition. Above 560?C, the RS became constant (5.4~6.0W/sq) again. Since the low-pressure, susceptor-based RTP system mainly uses gas conduction for wafer heating, variation in wafer backside emissivity by film structure has a very small effect on process results.
The phase transition temperature of Co/poly-Si was found to be ~40°C lower than that of Co/Si(100). The shift in phase transition temperature between single crystalline and polycrystalline Si is a fairly common phenomena in metal silicides [10]. In the self-aligned silicidation process, there are two types of metal silicide interfaces (i.e., metal/poly-Si in gate area and metal/single crystalline Si in source and drain areas). It is important to have a wide overlapped process window between Co/poly-Si and Co/Si(100) for process robustness. Although the RS change ratios vary for Co/poly-Si and Co/Si(100) in the silicide formation temperature region, process windows for both formation and anneal are overlapped in a relatively wide temperature range (Fig. 7). This wide overlapped process temperature window as well as backside emissivity (induced by backside film structure) independence will provide extremely repeatable and reliable process results in a device-manufacturing environment.
In most lamp-heated RTP systems, wafer temperature is directly monitored by optical pyrometer(s) and controlled through a sophisticated temperature controller during the process. Si wafer emissivity changes drastically as temperature decreases below 600°C [4], making wafer temperature control very difficult. Since the backside film structure also changes the effective emissivity of the wafer in a wide range, accurate wafer temperature measurement and control become even more difficult. In contrast, the susceptor-based RTP system measures and controls susceptor (SiC coated graphite) temperature using an optical pyrometer to provide the same thermal environment to incoming wafers regardless of backside film structure. The susceptor shows nearly blackbody optical characteristics (emissivity >0.95) and does not change its emissivity much as compared to Si wafers. Higher-emissivity material provides a stronger optical signal at a given temperature. By measuring the temperature of higher-emissivity material, we can improve the signal-to-noise ratio. As a result, susceptor temperature can be controlled very accurately. Below 700°C, heat transfer through gas conduction is the predominant wafer-heating mechanism. Ambient temperature control and wafer heating through gas conduction allow for a highly reliable, backside emissivity (induced by backside film structure) independent cobalt silicidation process.
Due to vacuum loadlock, dual wafer-processing capability, and efficient temperature ramp up/down characteristics of the Aspen RTP, throughputs of 90 and 50 wafers/hr are achieved for 45-sec and 90-sec processes, respectively. Steady-state power consumption for CoSi2 process temperatures (<700°C) is <2kwh (avg).
Summary
Very thin cobalt silicide formation and annealing were investigated using a susceptor-based low-pressure RTP system. TiN (10nm thick) capped cobalt films with three different thicknesses (7, 10, and 13nm) were studied. Cobalt silicide process sensitivity was investigated as a function of process temperature (350~700?C) and time (60~120 sec), Co film thickness, and backside film structure.
A production-worthy shallow silicide contact formation process has been demonstrated with backside emissivity independence using a susceptor-based low-pressure RTP system. A wide process window and excellent RS uniformity have been demonstrated for cobalt silicide process-integration steps. The NANU of typical TiN capped 10nm-thick cobalt films was <0.5% (1s). The process windows for the first step and second step CoSi2 annealing are 460~560°C and >600°C, respectively. n
Acknowledgment
The authors would like to thank J. Givens, A. Taranu, D. Whitworth, K. Johnsgard, R. Martin, and B. Mattson of Mattson Technology Inc. for useful discussions and encouragement.
References
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8. W.S. Yoo, A.J. Atanos, D.M. Whitworth, Jpn. J. Appl. Phys. Lett., accepted for publication.
9. W.S. Yoo, A.J. Atanos, 7th Int. Conf. on Advanced Thermal Processing of Semiconductors - RTP `99, Colorado Springs, to be presented.
10. S. Murarka, Silicide for VLSI Applications, Academic Press, New York, 1983.
Woo Sik Yoo received his BS from Dongguk University in Seoul, Korea, and MS and PhD in electrical engineering from Kyoto University in Japan. He also received his MBA from Western Connecticut State University. Yoo joined Mattson Technology as a senior product technologist in 1997, and is now working on RTP system characterization and process development, as well as managing the business development and strategic marketing for the product.
Ashur J. Atanos received his BS in materials engineering and MS in engineering from San Jose State University, both focusing on microelectronics. He has more than 10 years of experience in the industry and has been heavily involved with RTP. Four years ago, he joined Mattson Technology to develop a new-concept RTP tool. Mattson Technology Inc., 3550 West Warren Ave., Fremont, CA 94538; ph 510/492-6201, [email protected].
Jean-Francois Daviet received his PhD in physics in 1991 from the LETI / Institut National Polytechnique de Grenoble in Grenoble, France. He spent 18 months as a post-doc researcher at IMEC, Belgium, and then joined Matrix Integrated Systems as the manager of R&D for Europe. He is currently the technology manager of the RTP Group at Mattson Technology.