Technology News
07/01/1999
Wafer-level CSPs fabbed without wafer modification
Multichip Assembly, San Jose, CA, has developed a new method for wafer-level fabrication of chip scale packages (CSPs) that does not add fabrication or assembly processing steps to wafers before singulation.
Dubbed McCSP, this assembly process works with any wafer size and is done with conventional semiconductor processing equipment. Resulting CSPs can be truly die size (i.e., 1x chip size) and <0.8mm thick.
While officials at Multichip Assembly have not publicly announced a McCSP packaging cost/chip, Solid State Technology believes that this technology could result in cost savings of 50-60% compared to established wafer level packaging technologies that add ~$1.00/chip.
Briefly described, the McCSP process laminates a sheet of glass holding an array of traces and pads for the next level of interconnect to the active side of a completed wafer. A 3-5µm layer of clear nonhygroscopic adhesive is used for attachment. Etched vias in the glass align with the die bond pads. The wafer`s bond pads are connected to the array on the glass by bridging through the gap created by the glass and the adhesive.
 The McCSP structure ties solder balls to die bond pads through vias in a protective glass sheet that is laminated to a wafer. (Source: Multichip Assembly) |
Company founder Don MacIntyre says, "The beauty of this process is that it does not involve grooving, extra routing, or any other modifications to a completed wafer full of die, so we really cut risks typically associated with wafer level assembly operations. In addition, we do the whole process on a regular fab line."
The glass is matched to the coefficient of silicon thermal expansion to reduce flex of the silicon-glass assembly, thus avoiding related moisture problems with completed CSPs. Any mechanical differential between the silicon and glass is relieved by the adhesive layer.
Fabrication of the glass sheet involves cutting it to wafer size, etching vias, and metallizing with 500Å of sputtered Cr and 2000Å of Ni. A photoresist polyimide is applied, exposed to a mask pattern, and developed to form Cr-Ni traces and solder pads in a die-sized array on the glass. The glass pattern is cleaned to remove organics from the metal just prior to wafer attachment. The clear adhesive means ink-marked die from probing can still be identified after wafer-level assembly.
After glass-to-wafer attachment, a bake seals the structure. Photoresist is applied and developed to open only the vias and traces, leaving the solder pads covered. A subsequent plasma dry etch removes any adhesive from the traces and vias. When Al is deposited, it bridges through the vias and covers the Cr-Ni traces.
Finally, a polymer solder mask is formed to protect the circuit traces around the pads. After solder pads are thoroughly cleaned, the wafer-glass assembly is ready for attaching the next level of interconnect; alternatives include tin-lead solder balls for CSP or BGA applications, through metal bumps, or conductive polymer bumps. A final conformal coating prior to dicing enhances the reliability of the solder-ball side of the assembly.
Alternatively, the process can use Cu metallization with Au flashing, rather than Al, making it compatible with Cu IC interconnections; the glass needs no barrier layer to prevent copper diffusion. "Moreover, with or without a passivation layer over the die, the glass provides excellent circuit insulation and isolation from spurious signals, to which the next generation of superchips will be very susceptible," notes MacIntyre.
"With vias right over the pads on ICs, this packaging technique provides the absolute shortest path to the next interconnect level and thereby the least possible impedance for high-speed I/O," MacIntyre says. "Further, impedance can be controlled, for a given metal, by varying the glass thickness within 75-145µm and the array pattern."
While with standard IC packaging methods the cost of the package becomes a larger share of a CSP cost when a circuit is shrunk, McCSP costs remain in constant proportion with design shrinks.
Current McCSP outline and terminal layout is in line with Joint Electronic Devices Engineering Council (JEDEC) standards, with 0.3mm solder balls arranged in a 9x4 array for PC board attachment. However, the method can implement CSPs with much higher I/O counts. Also, the method allows fabrication of hermetic packages for military and space use.
Multichip Assembly is in negotiations to license the packaging method. As an option to license agreements, the eight-year-old package contractor plans to offer turnkey equipment modules for integration of the McCSP process with existing fab lines. - Pete Burggraaf
TSMC plans 300mm fab; rolls 0.18µm process
Taiwan Semiconductor Manufacturing Co. and affiliate Vanguard International Semiconductor Co. will break ground on what is expected to be Taiwan`s first 300mm fab in the spring of 2000.
TSMC has also disclosed details of its 0.18µm CMOS logic manufacturing process, which has already begun initial production.
The 300mm line is expected to begin production in 2002. A TSMC spokeswoman said the facility will begin work at the 0.13µm generation. It would likely migrate at least one more generation, to 0.10µm, and perhaps beyond. TSMC`s logic roadmap calls for 0.13µm production to begin on 200mm wafers in 2001, using a one-poly, eight-metal layer process with all-copper interconnect. This would seem to offer an ideal time frame, as 300mm work could begin with a relatively mature process, and then have the opportunity to migrate to the next generation a year or so after startup.
Anticipated investment for the facility is 60 billion to 70 billion Taiwan dollars (about $1.83 billion to $2.135 billion at recent exchange rates). No word was immediately available on how TSMC and Vanguard would divide the investment, but the spokeswoman said the output would likely be divided 50/50. Vanguard`s business is currently focused on DRAMs, while TSMC is the world`s largest dedicated foundry.
TSMC`s new 0.18µm process uses one poly and six metal layers, and provides operating voltages between 1.8-3.3 V. Initially all interconnect will be aluminum, but Q3 will see availability of a successor process in which the top two layers will use dual damascene copper with a tantalum nitride barrier layer. An FSG low-k intrametal dielectric material is used on the aluminum interconnect layers; standard silicon dioxide as an interlayer insulator and on the copper layers. Ken Chen, senior manager for new technology support and marketing, said TSMC development engineers found that copper did not provide enough speed improvement on the smaller interconnects typically found on lower layers, and that the aluminum-plus-FSG combination was more manufacturable. SiO2 is used for interlayers to provide better CMP compatibility.
The poly layer uses PVD-deposited cobalt silicide, rather than titanium, for its low and uniform sheet resistance at very small dimensions, said Chen. An RTP step fuses the CoSi with the transistor structures. Vias are tungsten, and a shallow trench isolation design is used. A dual gate oxide structure is available for operation at greater than 1.8 V; the standard 32Å layer can be increased to 50 or 70Å to provide 2.5 or 3.3 V tolerance for I/O, analog, and mixed-signal applications.
TSMC`s US senior director of marketing Roger Fisher noted that TSMC`s gate length of 0.16µm is slightly larger than the 0.13µm in IBM and Intel processes, and thus has lower drive current. This is an intentional tradeoff, reducing performance slightly in exchange for a far lower leakage current-0.1nA/µm compared to 3nA in Intel`s process-which greatly reduces heat generation and allows system designers to avoid fans and heat sinks, said Fisher.
 A TEM photo of TSMC's 0.18µm CMOS logic process. (Source: TSMC) |
Phase-shift photomasks will be used for critical layers such as contact layers, where additional depth of focus is desired, said Chen. The alternating-aperture masks are produced by TSMC`s internal mask shop; software from Numerical Technologies, Santa Clara, CA, is used to aid adaptation of customer designs. "We need to work closely with our customers` designers," noted Chen.
ASM Lithography 248nm steppers will be used to expose most layers on the 0.18µm devices; line pitch on metal layers ranges from 0.46µm on Metal-1 to 1.0µm on Metal-6. By the 0.13µm generation, however, Chen said, "We cannot live without 193nm [lithography]. We`re a preferred customer of ASML, and will get a 193 tool by the end of the year, the first in Taiwan. Our mask shop is working closely, and should be able to keep up the same pace."
TSMC`s 0.18µm process comes on line slightly more than a year after the firm`s 0.25µm capability, and TSMC expects to begin offering 0.15µm products a year from now. A 0.18µm mixed-signal process will be available late this year.
"We`ve been on a one-year cycle [since 0.35 micron in 1997]; we`ve been catching up," said Fisher. "At 0.18, we`ve caught up with the leaders." - Peter Dunn
SID `99: Display advances, challenges outlined
The largest of the large and the smallest of the small captivated attendees at the Society for Information Displays (SID) annual conference, held in mid-May at the San Jose Convention Center. Projection displays for digital cinema, and packaged head-mounted displays (HMDs) using liquid crystal on silicon (LCOS) LCDs, were the newest developments shown in non-direct-view FPD designs.
The last few SID shows revealed more fundamentally new FPD designs-such as field emission device (FED), plasma display panel (PDP), and organic light emitting diode (OLED) designs-to challenge LCDs in new FPD applications. This year`s show, however, was a reminder of how difficult it is to move from R&D to volume manufacturing in microelectronics.
- FED: The FED scene was relatively quiet. There were rumors of development delays at Candescent, San Jose, CA, with an expectation that partner (and major investor) Sony will need to play an active roll in trying to start up the company`s new high-volume fab in San Jose. Candescent acknowledged some technology hurdles in the development of its FED displays last year, but said, "these development issues have been resolved and significant improvements have been made in the company`s ThinCRT displays, as evidenced by the showing at SID in the Sony booth. The company is moving along with its original business strategy, which is to engage with strategic partners for manufacturing opportunities. Although Sony is one [possible] manufacturer, no announcements have been made." The company noted that it is "engaging with numerous world-class partners." Motorola didn`t exhibit at the show, despite a huge promotion for its 5-in. diagonal FEDs at SID `98.
- PDP: Phosphor development has progressed to the point that the displays have better lifetimes, but assembly operations continue to be expensive and low-yielding. Assembly hassles are the main reason that these attractive, bright monitors continue to cost more than $8000, with virtually no price cuts in 12 months.
- Microdisplays: Now well past proof-of-concept, microdisplay applications were revealed for many end-markets, such as personal monitors for games and PCs, and projectors for business or cinema. Most companies unveiled new designs featuring increased resolution, color, or integrated driver circuitry in the silicon backplane of LCOS approaches. The MicroOptical Corp., Westwood, MA, showed prototype eyeglass mounted displays. They feature a fiber optic cable channeling the image from a microdisplay, through the temple of a pair of glasses, to a small prism that floats in the center of one lens (a design featuring the prism integrated into the lens itself is promised). Full color VGA-resolution HMDs should arrive in consumer outlets in 1-2 years at about $400 retail.
- Digital cinema: Hughes/JVC and Texas Instruments demonstrated digital projection technology specified to equal the viewing experience of 35mm film. TI`s Digital Light Projector (DLP), based on three Digital Micromirror Devices (DMD), looked like it displayed slightly superior contrast and color depth, though both seemed comparable to film. It is expected that improvements to either technology will result in a viewing experience that eventually surpasses film.
- AMLCD: While most attention has focused on advancing driver circuitry (with low-temperature poly-Si, continuous grain poly-Si, etc.), filters, and polarizers to improve image quality, a Japanese start-up has a revolutionary development that could shake-up the industry. Hunet, Tokyo, Japan, developed rapid response three-color cold-cathode backlight that eliminates the need for color filters (which reduce brightness) and two-thirds of the pixels; custom driver circuitry synchronizes the backlight with the pixel array to produce full-motion, full-color TFT-LCDs. The company`s first products are segmented TN-LCDs for instrumentation displays. - Ed Korczynski
German consortium, ASML focus on 157nm lithography
Renewed clamor over 157nm optical lithography development activity is not just the domain of US-based SVG Lithography. In Europe, Dutch scanner supplier ASM Lithography is moving ahead with its own program, and the German Initiative for 157nm Lithography, led by project coordinator Carl Zeiss GmbH, Oberkochen, is underway.
This German alliance is seeing roughly 20% funding of the overall development costs (or 40% to 50% of pure research costs) from the German Federal Ministry of Education and Research, said project coordinator Rainer Garreis from Carl Zeiss. Much like other programs, the German project is concentrating first on optical materials for photomasks and optics, lens design concepts, and optical technologies. Basic R&D efforts are expected to extend until mid-2001 (see illustration). This will be followed by tool and process development with first production tools at the end of 2003.
European project partners with Carl Zeiss include Schott ML for optical materials, Lambda Physik for laser technology, Infineon Technologies AG (formerly the semiconductor group at Siemens AG) for process and resist development, and Jenoptik AG for the beam delivery subsystem.
"Basically by mid-2001, all puzzle parts must be in place: optical design completed, optical materials qualified, and mask manufacturability proven," Garreis noted. The biggest challenge areas for 157nm are in mask technology, resists, optical system layout, and purging issues, "in this line of order," he said. Transmission enhanced fused silica will be the Initiative`s material of choice for reticles, "if it is available in time and quality. We do not believe in the availability of this material in good enough quality as lens material. This means for the single lens elements, calcium fluoride will probably be the material of choice." The lens design for the 157nm tool will be decided next year, along with laser specifications. Garreis also said there are several possibilities for resists. "One promising line is adapting the CARL resist of Siemens for 157nm," he said. In addition, discussions are underway with International Sematech on how the two groups can collaborate on 157nm development.
 Roadmap of the German Initiative for 157nm Lithography. (Source: Carl Zeiss) |
ASML plans to pursue 157nm lithography, and will use the output of the German effort as an integral part of its development. ASML is partnering with Carl Zeiss for lenses, Philips for the tool platform, Hewlett-Packard for interferometers, and Cymer and Lambda Physik for lasers. ASML targets 2003 for a tool that will meet production requirements for 100nm lithography.
A key decision for the future of 157nm lithography revolves around lens design. According to Bill Arnold, senior scientist at ASML, "We have had a few discussions with Carl Zeiss on various lens alternatives. While an all refractive design with CaF2 is very attractive to us because it`s our background, there is a basic tradeoff that you have to make between the available optical materials and laser bandwidths; a fully refractive design needs perhaps 0.2pm bandwidth and right now 157nm laser technology is delivering 1pm."
Arnold admits that ASML has looked at "other possible lens designs including all reflecting and catadioptric approaches. "We have made a good engineering survey and we will be in a good position to make a final lens choice next year."
As for ASML`s platform for 157nm lithography, Arnold says, "It will be an extension of what we are now developing for advanced 193nm lithography."
Arnold says, "We don`t really know where 157 is going among other alternatives. On one end we have major efforts to develop 193nm lithography and on the other end we have key efforts in developing EUV and SCALPEL. It is really interesting to me to figure out where 157 fits in, as it has limited extendibility for the investment required."
In addition, all 157nm lithography development work is set against the backdrop of International Sematech, which is expected to make a final decision on whether to fund a 157nm lithography program this summer; a six-month feasibility study is underway at MIT Lincoln Labs. - Pete Burggraaf, Christine Lunday
SBC `99: I300I milestones, cycle time, spec-setting
SEMI`s second annual Strategic Business Conference, held recently in Welches, OR, offered a closer look at Lucent Technologies` system-IC strategy, development of IDT`s 0.18µm chip, and the accomplishments of the International 300mm Initiative.
During the April gathering, David Williams, VP of Cirent Semiconductor (a joint venture between Cirrus and Lucent), presented information on Lucent`s system-IC strategy. By optimizing design and manufacturing, the company achieves functional process modules that can be mixed-and-matched by system-chip designers. A standard digital CMOS logic process is the foundation, while additional processes can be added with minimal additional mask levels. For example, the company`s current 0.25µm process (with four levels of metal) can be expanded in four ways: Linear (four masks), BiCMOS (three masks), HD SRAM (three masks), and Flash (five masks).
To achieve faster cycle times in response to rapidly changing customer orders, Lucent has a new manufacturing logistics system with no finished goods inventory and rapid WIP transport; the target is one day for each mask level processed in the fab.
Len Perham, president/CEO of IDT, provided some relevant facts about his company`s new "SwitchSTAR" chip co-developed with Motorola and Micron. While it took 18 months to design, manufacture, and sample the new chip (which has 0.18µm design rules, and Leff of 0.13µm), it required a prior 18 months of working with partners and customers just to define the chip`s specifications.
A keynote luncheon speech by Derek Youngson, Intel assignee to I300I covered the results of the soon-to-expire consortium`s activities. I300I`s official three-year charter started in June, 1996, and as of June of this year it was expected to achieve several milestones, including 56 full equipment demos, 34 full 300mm standards approved, five metrology gauge studies, and initiation of joint activity with Selete, Japan`s 300mm program.
A 300mm team will continue to support a core toolset in the Sematech cleanroom beyond June, to continue work on standards, factory automation, and a small number of tool acceleration projects. Reliability for 300mm tools may still be a problem for the industry. Although mean time between fails (MTBF) for all tools except CMP exceeded the lowest performing comparable 200mm tool (from existing fabs), most tested 300mm tools didn`t meet even 50% of the more rigorous MTBF specifications desired by chipmakers. - Ed Korczynski
TI plans DMOS 4 upgrade
Texas Instruments will make a substantial upgrade to one of its 150mm wafer fabs, reportedly the DMOS-4 facility in Dallas, and adopt a minienvironment strategy for the facility during construction and subsequent operation.
The project represents as much as $30 million in revenue for Asyst Technologies, the Fremont, CA, supplier of SMIF minienvironments and equipment, and also marks one of the first uses of SMIF pods at a domestic facility owned by a major North American chipmaker.
A Texas Instruments spokeswoman said she could not provide details of the fab upgrade, but sources familiar with the project said it calls for the DMOS-4 facility to undergo a fast-track upgrade to 200mm wafers while advancing minimum design rules to 0.25 and 0.18µm from today`s 0.50µm levels. First tools are expected to start arriving around October, with revenue production on the new line starting just eight months later.
Adoption of the SMIF system will allow the 150mm line to continue operating during the upgrade process, said an Asyst spokesman, because the cleanroom will not have to be gutted for improvements.
"The linchpin of the strategy is the ability for any company to keep running an existing production line and keep their revenue stream while they transfer to a larger wafer size," noted Dennis Riccio, senior VP for global customer operations at Asyst. Virtually every new tool will be outfitted with SMIF capability; Riccio said "a high percentage" of the new systems would have their SMIF interfaces installed by Asyst on the fab floor, with "many others done on an OEM basis" by the tool producer.
This deal constitutes one of Asyst`s largest-ever domestic orders. Riccio said it could mark "the second wave of SMIF. The first wave was an evangelical task, which was very successful and the foundation for all our business in Asia. But we didn`t really engage with a lot of the big US guys." The TI work should "help us convince other companies," he said.
Riccio added that fab upgrades could prove to be an important business sector for Asyst in the next few years, as chipmakers grapple with the slow transition to 300mm and their desire to avoid building the last 200mm fabs. - Peter Dunn
UVTech unveils laser-based dry wafer cleaning
With an eye toward bringing laser-based technology to the wafer cleaning market, UVTech Systems, Wayland, MA, has unveiled the Mark II Discovery Laser Broom, a process development tool designed for use in research and development of UV-reactive dry cleaning processes for semiconductor production. The technology could replace wet cleans in a number of process areas.
Initial work on the Mark I Laser Broom began in 1995, shortly after UVTech`s founding, and continued through a cooperative development project with Praxair. That work tested the use of UV light plus reactive gases for wafer cleaning, researched various combinations of gases, and produced some preliminary process recipes, notes David Elliott, president/CEO of privately funded UVTech. A set of patents resulted, and UVTech has spent the subsequent years performing applications work, forming relationships with potential customers and partners, and developing an improved optical system for the Mark II.
Going forward, Elliott plans to take a deliberate, disciplined approach to the Laser Broom`s development, profiling and characterizing the manner in which the tool interacts with a variety of contaminants to develop a strong fund of process knowledge. "We plan to build a small number of tools, and get them into a small number of fabs," explains Elliott. "We`ll start with very light organics and particles, which are the easiest and allow us to work with green gases." The tool could also be used on heavier contaminants, like metallics, and post-implant debris.
The Broom utilizes a 248nm excimer laser light source, which is scanned across a wafer (200mm or smaller, although 300mm scaling is possible) in the presence of one or more gases, including proprietary formulations. One or more cleaning steps can be performed in situ, without damage to the wafer. A proprietary three-stage module will filter the exhaust to remove particulates and any toxic materials that may have been removed from the wafer; UVTech makes environmentally friendly operations a priority, and the Laser Broom is a near-zero emissions tool.
UVTech plans to present a paper on the Laser Broom at Semicon West in San Francisco, and is quoting delivery of Mark II systems for 1Q00. A Mark III system, designed for production use, will appear after additional process development is completed, likely in about two years, said Elliott. - Peter Dunn
TECH BRIEFS
Lucent Technologies` Bell Labs physicists have uncovered the nature of the defects that allow "electron escape routes" through very thin gate oxide layers in ICs. Yves Chabal, and colleagues Marcus Weldon and Kate Queeney, devised a method to grow silicon dioxide slowly-one fractional atomic layer at a time-watching the growth every step of the way. They accomplished this by causing silicon and water to react under ultra-high vacuum conditions, followed by ultra-slow oxidation at room temperature. The researchers combined infrared spectroscopy with state-of-the-art calculations provided by Krishnan Raghavachari to determine which atoms were present and how they ultimately joined together to form a continuous film; "the results showed how silicon and oxygen occasionally come together in unconventional ways, leading to the formation of microscopic defects," Chabal said.
NEC has completed the development of a new 0.18 and 0.15µm CMOS process for producing logic LSI system-on-a-chip devices. Dubbed CB-11, the process allows for the easy integration of on-chip DRAM along with logic. The 0.18µm process will allow for up to 34 million logic gates and maximum speed of 350MHz; the 0.15µm can accommodate 22 million gates at speeds up to 500MHz. Both feature five to seven metal layers, and internal operation at 1.5-1.8 V with 1.8-3.3 V I/O. Five types of packaging will be offered, including flip chip with up to 2500 pins, and chip-scale packaging with up to 600 pins. Volume manufacturing of the 0.18 and 0.15µm devices is scheduled to begin next January at the NEC-Yamagata subsidiary.
PATENT BRIEFS
A US district court jury in Texas has ordered Hyundai and its US-based affiliates to pay Texas Instruments $25.2 million in damages after finding Hyundai had willfully infringed two of TI`s patents related to methods for automatically transferring wafers and other workpieces between two or more workstations in an assembly line. The patent dispute arose after the two companies were unable to renew an expired cross-licensing agreement under which Hyundai had been licensing the technology in question, said a TI spokeswoman. Hyundai said the verdict is improper and contrary to the evidence. In addition, Hyundai has brought allegations against TI for patent misuse. A separate trial is being held to resolve the issue, and several other patent cases are pending between the companies.
Trikon Technologies, Newport, Wales, has received a US patent (number 5,874,367) for its Flowfill CVD process technologies, relating to the deposition of insulating layers. In work by Mitsubishi Electric Corp. researchers, the process has been shown to be capable of gap fill below 0.1µm, to self-planarize, and to integrate with a dielectric constant of 2.75.
TECH BRIEFS
Under a licensing agreement with Mitsubishi Electric Corp., Clariant`s AZ Electronic Materials business will sell a new chemical shrink agent capable of reducing 0.2µm via holes to 0.1µm using existing KrF excimer laser tooling and standard photoresists. The chemical shrink and process, also known as resolution enhancement lithography assisted by chemical shrink (RELACS), was jointly developed by Mitsubishi and Clariant. The material is processed with coat, bake, and rinse steps following wafer patterning, and is capable of working in the i-line exposure range, shrinking 0.35µm via holes to 0.20µm.
Soitec and Philips Semiconductors, Eindhoven, the Netherlands have jointly created a thin-film SOI Smart Power technology for consumer applications. The bipolar-CMOS-DMOS technology (a single-poly, double metal technology targeted for 12V to 60V applications) was developed on a bonded SOI Unibond wafer, manufactured using Soitec`s Smart Cut process. The technology uses a 1.5µm active silicon layer on top of a 1µm layer of buried oxide.
Sumitomo Metal Industries, Osaka, and Mitsubishi Materials Corp., Tokyo, are forming a new joint venture company to develop and manufacture 300mm wafers, with work beginning this month. Sumitomo Metal (formerly known as Sumitomo Sitix) and Mitsubishi Materials Silicon, the silicon manufacturing arm for Mitsubishi Materials, will each transfer existing 300mm development and pilot production divisions to the new joint venture, which will manage the 300mm businesses. The two firms have a total 300mm manufacturing capacity of 15,000 wafers/month, but plans call for a new 300mm manufacturing plant with a capacity of 100,000 wafers/month to be established around 2002.