Etch challenges of low-k dielectrics
06/01/1999
Unit processes now exist to plasma etch the main categories of possible interconnect low-k dielectrics. Integration challenges and trade-offs remain for all films, though all can be etched within a dual-damascene process flow. Controllability and cost of the integrated process will determine material choice, since unit processes are relatively similar.
A wide variety of low dielectric constant (low-k) materials are being investigated for use as interconnect dielectrics in place of traditional oxides for high-performance devices. New materials are needed to reduce the capacitive component of RC interconnect delays [1, 2].
There are basically two implementation strategies for incorporating low-k materials [3]. Some semiconductor manufacturers have already implemented Cu dual-damascene process architectures with oxide as the dielectric, and are now evaluating low-k dielectric materials. Other manufacturers plan to use traditional aluminum with low-k materials, and will implement copper dual-damascene structures in a later phase.
Low-k materials may present challenges both from a material integration and an etch perspective. Some low-k materials can be etched with a slightly modified oxide etch process; others will require completely new process regimes. In addition, certain etch and strip procedures will need to be optimized for specific dielectric/metal choices. This article reviews the etch challenges for different low-k dielectric materials and the various approaches used for successfully etching these materials. Also, a discussion of the methods by which the discrete etch steps are integrated into dual-damascene process architectures will be presented.
Low-k dielectrics
Low-k dielectric materials can be categorized as follows: doped oxide, organic, highly fluorinated, and porous materials. The porous class of materials introduces microporosity into the other base materials to reduce the net capacitance. Low-k materials can be deposited either by spin-on or CVD methods. Porous materials are typically spun on, with controlled evaporation of solvent providing the desired pore structure. Some specific examples of the different categories of low-k materials are listed in the table.
The determination of which low-k dielectric is best for a fab will depend on integration and etch issues, capital and materials costs, and the installed equipment base. For example, many chip manufacturers prefer that all low-k dielectrics be deposited by CVD, while others may be inclined to use spin-on dielectrics. Due to the wide variety of factors involved, it is unlikely that a single low-k dielectric will dominate the low-k market.
Etch challenges
Most of the materials listed in the table can be etched on either a medium-density plasma etch system using capacitively coupled plasmas, or on a high-density plasma etch system that utilizes either inductive, helicon, or ECR plasmas. Development activities targeted toward extensive etch characterizations of all of the low-k material types are under way. Results will be presented for both a medium-density plasma etch system, the 4520XLE, and a high-density plasma etch system, the TCP 9100PTX, both from Lam Research.
Doped oxides. Fluorine doped oxide (or fluoro-silicate glass, "FSG") process flows can be relatively easily incorporated into existing etch and CVD equipment, requiring only minor modifications to existing processes. The oxide etch processes used for TEOS may be used for FSG, delivering etch rates up to 20% higher than oxide since fluorine doping weakens the S-O average bond strength. A commensurate increase in selectivity to silicon nitride and to photoresist is also achieved.
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A typical etch chemistry uses a mixture of fluorocarbon gases (such as C4F8 and CF4) to control the carbon-to-fluorine ratio, with CO to scavenge free fluorine (as an additional means of controlling the carbon to fluorine ratio), and Ar as the diluent. High selectivity to Si3N4 is achieved by increasing the C4F8:CF4 ratio, and optimizing the wafer temperature. Etch rates >10,000Â/min. and profiles greater than 88?, with a high selectivity to silicon nitride, can be achieved (Fig. 1).
Hydrogen doped oxides (e.g., HSQ) are also etched using an oxide etch baseline process. Modifications to the process are made to meet the etch rate and profile specifications using the same control parameters as above. High levels of H-doping (>15%) lower etch rates, and the profile may become tapered. Both effects can be compensated for by the addition of a low amount of O2 flow in the etch chemistry. Optimization of the oxygen flow during the etch is critical since, in certain instances, large amounts of oxygen in the plasma can remove hydrogen from the sidewalls and increase the dielectric constant [4, 5]. Also, loss of HSQ passivation due to O2 attack in oxide sandwich structures can result in undercut or bowing of the profile.
The effect of O2 plasmas on hydrogen-doped oxides is even more critical when stripping the photoresist. An oxide cap layer can be used to protect the top surface during the ash, and this cap layer also acts as a barrier to minimize moisture absorption by these films. Since high strip temperatures employed by many commercial photoresist strip systems also increase hydrogen attack of the HSQ, precise wafer temperature control is essential. To limit hydrogen removal from HSQ materials, in situ photoresist strip in the etcher may present compelling advantages due to the excellent wafer temperature control offered by etch systems.
Like hydrogen-doped oxides, some carbon doped low-k materials such as MSQ may also be attacked by oxygen during strip due to the formation of a porous surface layer [6]. Unlike fluorine- and hydrogen-doped films, carbon-doped materials may require significant modifications to the oxide etch process, depending on the doping levels of C and H in the lattice. The dielectric constant is related to the doping level, the nature of Si-C and Si-H bonding, and film density. All of these film properties alter the etch characteristics of the film, and therefore an acceptable etch solution is obtained by optimizing parameters for the actual film composition.
For instance, a conventional TEOS etch process that is selective to Si3N4 will give unacceptably low etch rates for carbon-doped oxide films. One way to obtain an acceptable etch rate is to combine a fluorine-containing oxide etch with an oxygen-containing organic etch. The addition of O2 increases the carbon-doped oxide etch rate, but this process change also increases the photoresist and Si3N4 etch rates, and thereby degrades selectivity to photoresist and the nitride barrier.
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The challenge is then to develop an etch that preserves selectivity to the Si3N4 barrier layer. Some options include reducing the CO flow or the C4F8:CF4 ratio, both of which also improve etch rate, as an alternative or supplement to O2 addition. The object is to develop an etch process that provides good rates with the highest selectivity to Si3N4. Promising results on carbon-doped low-k dielectrics have been obtained by optimizing each of the described parameters for the film under investigation (Fig. 2).
Organic materials. Organic materials can be etched with either an O2 oxidizing or an H2 reducing process. These gases can be mixed with a diluent and an additional gas which provides sidewall passivation. Such etch processes for organic materials typically provide high selectivity to silicon dioxide and nitride stopping layers and barriers. Their selectivity to photoresist is only around 1:1, however, so silicon dioxide or silicon nitride hardmasks are used with these materials. The main etch challenge is to control the faceting of the hardmask while maintaining a high etch rate and vertical profile.
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Since pure O2 processes tend to etch most organic materials isotropically, vertical profiles are maintained by tailoring the amount of passivation and physical bombardment [7]. The facet etch rate of the hardmask is determined mainly by the ion energy flux to the wafer (proportional to the product of the ion energy and the ion flux). By operating in a low ion energy flux regime, the hardmask facet etch rate can be reduced. However, lower ion energy typically results in less anisotropic etching, and hence the need for a gas that provides some sidewall passivation (Fig. 3).
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Using the control parameters discussed above, optimized processes can be developed for various structures depending on the process architecture. Trench and via structures (the building blocks of the damascene process) in the SiLK semiconductor dielectric show good profile and CD control, with minimal hardmask faceting (Fig. 4). These processes have been optimized to produce a slight taper that is beneficial for metal fill.
One of the challenges of using organic materials is the need to strip the photoresist without attacking the underlying low-k organic material. Wet chemistry methods are typically used for photoresist stripping, although dry strip processes are preferred and are under active development. Since etch rates are similar between photoresist and organic low-k materials, the incoming photoresist may be optimized such that it is removed during the etch, resulting in process simplicity and cost savings.
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Highly fluorinated films. Highly fluorinated films may be etched with processes similar to those used for organic films. Some highly fluorinated films actually etch faster than the organic films with proportionately higher selectivities to hardmask and barrier layers. Figure 5 shows a trench in a Parylene AF4 film that was etched with a medium-density, capacitively coupled reactor. Vertical profiles with minimal faceting are illustrated.
Highly fluorinated films probably present fewer etch challenges than most films discussed so far. However, integration of these films into copper dual-damascene process flows presents significant difficulties. These films present the same challenge as organic films with respect to photoresist stripping. In addition, these films are typically very reactive with Ta and Ti, which are the primary constituents of the copper barrier layers. The high reactivity of these films has limited their adoption by most chipmakers. Nevertheless, because fluorinated films typically have the lowest dielectric constants, they may be reconsidered if an alternative barrier layer can be found that is less reactive with fluorine.
Porous materials. Porous materials using most of the base materials discussed thus far are also being considered to achieve even lower dielectric constants than the constituent materials. These materials are under development for <0.10µm design rules, since dielectric constants between 1.0 and 2.0 can be obtained. Oxides, doped oxides, organics, or even highly fluorinated materials will be used as the constituent materials with the appropriate pore morphology.
It is expected that the processes used to etch these films will be the same as those used on the bulk materials. This has been demonstrated by etching Nanoglass, a porous oxide. The etch rate was found to be inversely proportional to the film density. The film had a porosity of ~70% and the etch rate was approximately three times faster than TEOS. Since the etch process can be the same as that for the base material, the higher etch rates in porous materials also give higher selectivities to masks and barriers.
One concern with porous materials is that the composition of the pore surfaces may be different from the bulk material. For example, porous carbon-doped oxide films may have higher organic content on the surfaces of the pores. As the porosity increases, the average organic content of the films also increases, and the etch process would need to be adjusted accordingly.
Dual-damascene structures
Dual-damascene etching creates trenches for lines and holes for vias, which are then simultaneously metallized to form the interconnect wiring. Other etch processes often need to be integrated in with these basic unit processes. Depending on the specific materials used and their integration requirements, etch steps are needed for antireflective coatings (ARC), hard masks, and other thin barrier layers. For example, the barrier layer at the bottom of the via must be removed to allow electrical contact between metal layers. An integrated photoresist strip is also desirable to reduce the number of chambers required for damascene processing. All of these processes must be integrated to provide the best technical capability, with the lowest cost of ownership. From the perspective of manufacturing simplicity and flexibility, it is desirable to do all of the processing in situ in one etch chamber.
Many damascene process flows depend upon an intermediate etch stop layer to control the trench etch, and also serve as a hardmask providing CD control for underlying vias. Etch stop materials have relatively high k values (~4 for oxide, ~7 for nitride), however, so the layer must be as thin as possible (or eliminated entirely) to keep the overall capacitance low. If the etch stop layer is eliminated, then the etch process must be very robust (in terms of etch uniformity, trench shape, profile, CD control, etc.) for high repeatability under manufacturing conditions.
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The sequence of these basic etch steps defines a damascene process flow as self-aligned, via-first, or trench-first [8]. As Fig. 6 illustrates, the sequences begin with a different etch, but all three sequences end with the same dual-damascene structure. The different damascene schemes pose different etch challenges.
Self-aligned. In the self-aligned approach, the intermediate stop layer is patterned for via after the barrier nitride, via dielectric, and the intermediate stop layers have been deposited. The stop layer is then etched with the via pattern, and this layer serves as a hard mask for the via etch in a subsequent step. The trench dielectric and ARC layers are then deposited and patterned for the trench. The trench and via are then etched in the same etch operation - the trench etch stops at the intermediate etch stop layer, while the vias are etched through the patterned hard mask in the stop layer and stop on the barrier nitride.
Because self-aligned vias require almost perfect trench-to-via alignment, this sequence is not widely used. With respect to etch, the challenge is to maintain a very high selectivity between the dielectric and intermediate stop layer when etching the via.
Via-first. The via-first sequence requires that the via is masked and etched through both the trench and via dielectric and the intermediate etch stop (if one is used), stopping on the barrier silicon nitride. The wafer is then re-patterned for the subsequent trench and this pattern etched, stopping on the intermediate etch stop layer. In some cases, the via is covered by a photoresist or organic ARC plug that protects the via and the underlying barrier nitride during the trench etch.
The specific challenges associated with via-first etch include: controlling profiles and CDs in higher-aspect-ratio features than those seen for trench-first or self-aligned; obtaining sufficient selectivity to photoresist when etching doped oxide materials; opening the intermediate etch stop without losing CD control for organic and highly fluorinated films; and attaining high selectivity to the silicon nitride barrier if there are no photoresist or ARC plugs in the vias. If there is no intermediate etch stop layer under the trench, the trench etch must be very uniform with a flat etch front, and the subsequent via etch should provide tight CD control.
Trench-first. In the trench-first sequence, the trench is masked and etched through the dielectric with stop on either an intermediate etch-stop layer or at a timed depth (if an etch-stop layer is not used). The via pattern is then aligned with the trench and etched through any hardmask (if there is one) and the trench dielectric (if there is poor alignment) followed by the via dielectric to the nitride barrier layer. The possibility of misalignment between the via and the trench means that a long overetch may be necessary.
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The specific etch challenges associated with trench-first flows include: achieving a very uniform trench with a smooth flat etch front if there is no intermediate etch stop layer, and maintaining via CD control if there is no intermediate etch stop layer, especially with organic and highly fluorinated films.
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Etch solutions applicable to all of the damascene structures illustrated above have been demonstrated for a large number of low-k materials. These have been integrated with ARC open and hard mask open, as well as barrier nitride removal on 4520XLE and TCP 9100PTX etch systems. The results for fully developed damascene structures implemented on BCB and SiLK respectively are illustrated in Figs. 7 and 8.
Conclusion
The unit processes for etching various types of low-k materials were reviewed in terms of etch challenges and available solutions. The etch processes used for doped oxides are similar to conventional oxide etch processes, with the exception of carbon-doped materials. Carbon-doped oxide films are etched by optimizing the film characteristics together with etch parameters. For organic and highly fluorinated materials, process regimes with oxygen or hydrogen in the plasma chemistry are used, together with suitable passivant and diluent gases. Porous materials etch with significantly higher etch rates than the corresponding base materials, with the etch rate being inversely proportional to the film density. The different dual-damascene architectures were discussed in terms of the etch requirements they drive, and how the basic etch unit processes are successfully integrated into dual-damascene structures.
The final selection of a low-k film, including alternative barriers and etch stop films, will be decided more by overall integration issues than by etch capability. Due to the uncertain nature of the low-k material choices, versatile etch systems that provide wide process windows and can operate in different process regimes re-quired for current and future low-k materials will be advantageous to chipmakers.
Acknowledgments
All of the work sited in this review was carried out by researchers at Lam Research Corp., Sematech, and other partners. The authors would particularly like to recognize the contributions of Sue Ellingboe, Janet Flanner, Christine Janowiak, John Lang and Eric Wagganer of Lam Research Corp, and Scott Bass, Chris Foster and Ashley Taylor of Sematech, whose data has been illustrated in this article. Also thanks to Ganesh Rajagopalan, Sematech; T.S. Ravi, Novellus; Oana Leonte, AlliedSignal; and Mike Mills, Dow Chemical Co., for useful discussion.
HOSP and FLARE are trademarks of Allied Signal, Parylene AF4 is a trademark of AlphaMetals, SilK and BCB are trademarks of Dow Chemical Co., Nanoglass is a trademark of Nanopore Inc., and PAE-2 is a trademark of Schumacher Co.
References
- M.T. Bohr, "Interconnect Scaling - The Real Limiter to High Performance ULSI," IEDM Tech. Digest, p. 241, 1995.
- O.S. Nagawa, et al., "Impact of Low-k ILD and Cu on Circuit Performance," Proc. Mater. Res. Soc., 1996.
- W.W. Lee, P.S. Ho, "Low Dielectric Constant Materials for ULSI Interlayer Dielectric Applications," MRS Bulletin, Oct. 1997.
- N.P. Hacker, "Organic and Inorganic Spin on Polymers for Low Dielectric Constant Applications," MRS Bulletin, Oct. 1997.
- M.J. Loboda, G.A. Toskey, "Understanding Hydrogen Silsesquioxane-based Dielectric Film Processing," Solid State Technology, p. 99, May 1998.
- J. Waeterloos, "The Integration of Low-k Material with Organic Content in a Non-Etchback Process," Advanced Metallization and Interconnect Systems for ULSI Conference, organized by UC Berkeley, Portland, Oct. 1995.
- M. Setton, et al., "Etching of Organic Low-k Material for Copper Dual Damascene ULSI," presented at IITC, May 1999.
- G. Hills, et al., Semi Technical Symposium, Semicon Korea, 1999.
Authors
Ian Morey received his PhD in plasma physics from the Australian National University and completed post-doctoral fellowships there and at UC Berkeley. He is a program leader at Lam Research Corp.
Ashish Asthana received his MS and PhD degrees in materials engineering from the University of Illinois. He is senior product manager at Lam Research Corp., 4650 Cushing Pkwy., Fremont, CA 94538; ph 510/572-4878, e-mail [email protected].