Issue

Inkless assembly solves these problems because it uses electronic wafer maps instead of ink to classify good and bad die. In addition, inkless assembly enables software-driven material inventory tracking and gives process control engineers a usable form of history that can help them determine yield loss.

Briefly described, inkless assembly means creating a computer image of location and test results (Fig. 1) for each die on a wafer and transferring this "map" and its wafer to assembly (Fig. 2). In assembly, the accept-reject function of pick-and-place systems is map-driven rather than controlled by an optical detector. This improves throughput by eliminating the overhead of detection, and results in faster cycle times and lower cost.

Despite these advantages, the implementation of inkless assembly worldwide is <20%. Yet, greater application may come from drawing on system experience and a better understanding of the factors that have held back use of this technology. Today, there is a set of recommendations that can help smooth any transition from ink to inkless assembly.

Barriers to overcome

Good knowledge about system configuration (see "Software and system considerations"on p. 120) should help address the human anxiety about wafer-mapping reliability, which has been the biggest factor behind the reluctance to adopt inkless assembly. Consider that a cassette of wafers at probe represents a substantial investment in potential revenue for a company. Marking with ink dots during wafer sort is a solid physical process. It is a simple task for a pick-and-place system to find "uninked" good die at assembly. On the other hand, with an electronic wafer map, what happens if data are corrupted or lost or if the pick-and-place system uses the wrong map? In addition, and perhaps even more damaging, what if no one catches the error and hundreds of nonfunctional or poor quality ICs are packaged? Today`s semiconductor manufacturers are just as concerned with quality as with basic manufacturing costs.

Clearly, without proper attention to detail at a number of points, electronic wafer mapping can have problems. To correlate a digital map with a wafer, for example, there must be a simple, unambiguous way to orient the wafer on pick-and-place systems. In part, it is obvious to use the wafer`s flat or notch; however, past approaches to mapping sometimes did not include this information because it was erroneously assumed that the flat or notch would always be at the bottom. When flat or notch information is included, it can be inaccurately interpreted during map translation. Knowing the flat or notch position will only provide gross positioning information.

It is equally important to provide a good, unambiguous (e.g., optically unique) reference point on each wafer. While today`s pick-and-place and wafer-probing systems have vision-based subsystems capable of identifying such reference points, most fabs have been reluctant to give up the silicon real estate they need. (This is an ownership issue; if fab managers were responsible for inkless sort, references would start showing up tomorrow.)

Instead of optically unique references, pseudo-reference points are often used, adding risk and uncertainty to the process. Alternatively, in lieu of reference points, trained assembly operators manually "teach" the equipment about references. For example, the intersection of the first row and column of die on a wafer may be used. This approach is likely to continue for the next few years due to the length of time that it takes to implement the necessary process changes to automate references.

Another challenge is the multitude of formats for wafer maps. Virtually every prober-tester combination provides a different wafer map output. The industry`s SECS II wafer map standard provides some guidance, but it is a communications protocol, not a file format.

Many semiconductor manufacturers have been forced to define their own internal standards, often with the help of third-party experts, before deploying inkless probe technology. For example, Kinesys` Assembly Line Production Supervisor ([ALPS], Fig. 3) supports 55 different map converters for various process tools and customer applications.

What the industry really needs is an electronic map standard for all equipment, from wafer sort through assembly. Then everyone could use probe data as soon as possible after creation, without redundancy and the cost of reinvention.

Making the transition

Moving to inkless assembly is not something that can be done in isolation. Most of the recommendations that follow require close coordination between a fab, wafer sort, and assembly.

In addition to the recommendation above, the assembly facility needs a way to positively verify ID information before a wafer gets to die-attach, and a method for operators to edit incorrect information. Editing also allows operators to tag damaged die found during post-probe optical inspections. As noted earlier, most semiconductor vendors are under considerable customer pressure to maintain high quality levels, and can be removed from qualified vendor lists if they ship defective products.

It`s also necessary to agree on a process that guarantees there are no duplicate wafer IDs. Here, one method is to use Semi`s OCR standard. However, the Semi algorithm relies heavily on a two-digit checksum correction scheme that can be damaged during wafer processing. Electroglas and other probe vendors have been able to overcome part of the problem with new vision algorithms, but the industry still needs to improve on its age-old, two-digit standard to prevent incorrect data from reaching assembly. A better method, using cyclic redundancy check for example, could provide more robust IDs to help eliminate this problem.

Conclusion

Inkless wafer mapping between probe and assembly can provide significant productivity gains in IC manufacturing. Yet it has not been widely adopted because implementation schemes have not adequately addressed concerns and risk, associated with electronic maps being separated from the wafers they represent. The key to its implementation, however, lies in greater communication between the engineering groups involved. n

Acknowledgment

We thank Karl Hallin of Electroglas and Daryl Rawnsley of National Semiconductor.

Howard Ignatius received his BA from the University of Minnesota. He has been involved with semiconductor test for 23 years, and has served on Semi`s manufacturing-test steering committee, prober standards task force, and PSEM task force. Ignatius is an information product marketing manager at Electroglas, 2901 Coronado Dr., Santa Clara, CA 95054-3204; ph 408/727-6500, fax 408/982-8025, e-mail [email protected].

David Huntley received his BSEE from Bristol University, UK. He has worked on software automation and standards development for front- and back-end applications. In 1992, Huntley established Kinesys Software Inc., 6 Petaluma Blvd., N. B8, Petaluma, CA 94952;ph 707/766-8855, fax 707/766-8196, e-mail [email protected].