Buried layer substrates: Economically enhancing device performance
06/01/1999
Buried layer substrates formed by high-energy implantation and rapid thermal annealing are an attractive alternative to epitaxial substrates where high performance is required at lower cost. The heavier p-type doping and close proximity to the active devices make buried implanted layers much more effective than epitaxial wafers in eliminating transient latch-up events. The unique defect control ability of buried layer substrates lowers diode leakage and improves gate oxide integrity relative to unimplanted substrates. The heavy p-type region of a boron buried layer implant is also effective at gettering metallic contaminants such as copper.
High-dose buried layer (HDBL) substrates are beginning to enter mainstream integrated circuit processing, after several years of research and development. A buried layer is a heavily doped region of the same conductivity type as the substrate that is placed beneath the active device regions by ion implantation. Both the doping and damage characteristics of HDBL influence device performance. Buried layers are an important advance in substrate engineering, as the substrate itself undergoes special processing to ensure maximum circuit and device performance.
HDBL structures are easily integrated into standard CMOS processing with the additional steps of an implant, a rapid thermal anneal (RTA), and an optional cleaning step in between. These additional steps can be done either before or just after shallow trench isolation formation. The most common implant is boron at 1.5-2.0MeV (for p-type substrates), but occasionally is phosphorus at 2.5-3.5MeV (for n-type substrates). In either case, the optimal implanted dose varies between 5 x 1014 and 1 x 1015cm-2, which forms a highly doped layer ~1.5-3.0?m below the silicon surface. The buried layer must be implanted deeply so that the final dopant profile (after all thermal processes) does not counterdope the retrograde well of opposite conductivity, which results in low well-substrate breakdown voltage. A high dose (1 x 1015 cm-2) is recommended to optimize device performance.
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There is no photoresist on the wafer during the implant, so there are no additional lithography costs or photoresist outgassing issues during implantation. The post-implant RTA soak is 1000-1150?C for 10-30 sec. If the HDBL sequence is done prior to STI formation, it may be possible to anneal the buried layer implant and the trench simultaneously, eliminating an additional thermal process. Normal CMOS processing resumes with the retrograde well formation.
Latch-up control
The major circuit enhancement of the HDBL structure (Fig. 1) is the almost complete suppression of latch-up, a failure mode in CMOS circuits. To prevent latch-up, the trigger current must be as high as possible; trigger current is affected by many factors [1], but decreases steadily with decreasing n+/p+ spacing when all else is constant. Hence latch-up becomes an increasingly severe hazard as circuit packing density increases with each device generation.
If a minimum voltage (Vholding) is higher than VDD, the circuit cannot remain in the latched-up state after the transient noise has dissipated. However, even transient latch-up events will cause data loss and system instability, and have the potential to damage interconnect lines permanently. Despite the steady reduction in supply voltage with shrinking geometries, the only way to eliminate disruptive events is to engineer the circuit`s trigger current to exceed any expected transient current.
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The best way to maximize the current required to trigger latch-up is to prevent the transient output current from feeding into the latch-up structure by shunting this current to ground. This has traditionally been accomplished using the heavily doped substrate of an epi wafer, which acts as a low-resistivity ground plane in contact with the p-well. For this strategy to be effective at small geometries, it is crucial that the ground plane be as close to the active circuit elements as possible [2]. However, epi thicknesses of ~2.0?m appear to be a practical lower limit, before dopant diffusion from the substrate degrades capacitance and breakdown voltages in the devices.
HDBL structures replace heavily doped epi substrate as ground planes. Because implant energy is easily controlled, implantation can place a ground plane much closer to the n-well. Increasing the doping of the ground plane also enhances its ability to shunt current. The peak buried layer doping of 2 x 1019cm-3 exceeds that of most epi wafer substrates (1 x 1019cm-3). The combined effects of these improvements result in the highest trigger currents ever reported [3]. Figure 2 shows the latch-up trigger currents on bulk silicon as a function of buried layer dose (with epi silicon shown for comparison). The HDBL trigger current is superior to both epi and unimplanted bulk silicon, due to its unmatched current shunting ability.
Diode leakage control
In addition to the circuit benefits of latch-up prevention, HDBL substrates improve device performance by reducing source/drain diode leakage currents. Figure 3 shows leakage currents of large area n+/p and p+/n diodes fabricated on bulk and buried layer substrates. The diode leakage at low buried layer doses exceeds the controls, while at higher doses the leakage falls sharply with increasing dose, consistent with earlier reports [4-6].
Buried layer substrates affect diode leakage by altering the defect morphology in the region from the silicon surface to the buried layer peak depth. The final defect structure depends on both the buried layer dose and the soak temperature of the first thermal process after the implant. A high-dose, high-energy implant produces a large number of excess interstitials (primary defects) at the peak depth region. At moderate anneal temperatures, these interstitials form threading dislocations that extend out from the peak depth; the density of these defects increases with increasing implant dose, while the size of the defects decreases with increasing dose [4, 7]. As a result, the defect density in the near surface region (where the p-n junctions are located) first increases and then decreases as the buried layer dose increases.
At doses up to a threshold of ~3 x 1014cm-2, the increasing defect density results in increased diode leakage. For this reason, low-dose buried layers are very difficult to integrate successfully into advanced integrated circuits without the use of very high temperature (~1150°C) anneals. Above the threshold dose (3-10 x 1014cm-2, depending on annealing conditions), the average dislocation length eventually becomes small enough that dislocations do not extend to where they can induce leakage. The sensitivity of the defect morphology to moderate temperature annealing conditions decreases as the dose increases, disappearing almost entirely at 1 x 1015cm-2. For buried layer implants followed by higher-temperature anneals (>1050°C), the defect structure is different: secondary defects form a network of stable, extrinsic dislocation loops confined to the peak damage region of the buried layer implant. The density of these loops is proportional to the implant dose [8]. Since threading dislocations are not observed and diode leakage is lowest, high-temperature annealing after the HDBL implant is recommended to maximize the process window.
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Figure 3 clearly shows that HDBL substrates reduce diode leakage (and presumably dislocation densities) to levels below the control wafers. The likely cause is the excess vacancies in the near surface region resulting from the HDBL implant. Though most vacancies recombine with interstitials after annealing, some combine with dopant atoms or other vacancies to produce semi-stable clusters; these clusters can mitigate the effects of excess interstitials introduced during subsequent retrograde well implants [9].
This leakage reduction, when combined with aggressive scaling of shallow junctions by ultra-low energy implants, may reduce the need for punchthrough suppression implants in future CMOS devices. Because they do not contain vacancy clusters, dislocation loops, or other strain fields, epi substrates are not capable of similar diode integrity improvements.
Gate oxide integrity
Figure 4 shows the effect of an HDBL substrate on the time to breakdown of a 7nm gate oxide using a constant current stress test. Moderate dose buried layers produce outlying data points indicating poor gate oxide integrity (GOI), while the HDBL substrate gives a nearly straight line on a Weibull plot. Figure 4 also suggests that HDBL substrates should improve GOI compared to bulk wafers. The HDBL mechanisms for improved GOI include the interstitial gettering effects of the excess vacancies, and the impurity gettering effects of the dopant and defects at the buried layer peak depth. Additionally, HDBL structures getter oxygen very effectively near the surface, preventing the formation of oxygen precipitates [10]. Oxygen precipitates in this region can result in oxidation-induced stacking faults that reduce GOI.
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Although modern wafer fabrication facilities are extremely clean, effective gettering of metals is still important for successful device fabrication and good GOI. Figure 5 shows the effectiveness of an HDBL substrate at gettering copper. Copper was implanted (150keV, 1 ? 1013cm-2) into a wafer with both a boron HDBL (1.5MeV, 1 x 1015cm-2) and a silicon implant (0.7MeV, 1 x 1015cm-2). After RTA processing (1100?C, 30 sec, 25?C/sec ramp rate), the copper is heavily segregated to the B peak, even though the Si peak was encountered first during diffusion. This indicates that copper is gettered in silicon by chemical rather than mechanical means.
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Fully 91% of the implanted copper is segregated at the boron peak; this would have been higher if not for the 6% trapped at the silicon peak. The ability of HDBL substrates to segregate copper is an attractive feature with the increasing use of copper metallization. HDBL structures have been shown to getter iron, nickel, and other impurities. Iron [11, 12] and copper [13] are gettered by heavy p- type doping of the buried layers (segregation gettering), while nickel [13] is gettered largely by the strain field associated with the residual implant damage (proximity gettering).
Summary
HDBL substrates are easily prepared on commercially available equipment. A 1 x 1015cm-2 dose can be implanted at the rate of 38 wafers/hr (200mm wafers). The total additional cost for the HDBL preparation sequence (implant, clean, RTA) is $5-11, scaling largely with buried layer dose. About $2/wafer is saved if the HDBL anneal is integrated with the trench anneal. A high dose (1 x 1015cm-2) is recommended to optimize latch-up resistance, diode leakage, GOI, and impurity gettering.
The deposition of a high-quality epitaxial layer is a relatively expensive step in a typical CMOS manufacturing process. Although epi silicon is deposited on only a fraction of the wafers processed worldwide, concerns about performance in advanced logic devices have led to increased use of epi silicon in recent years. The HDBL process described above saves ~$40/200mm wafer over an epi process, with almost no additional process complexity.
The table compares the costs and performance of HDBL substrates to traditional alternatives. Significant cost savings result if devices built on epi silicon to avoid latch-up are moved to HDBL substrates. For low-cost devices currently fabricated on bulk silicon, HDBL substrates can eliminate latch-up concerns for little additional cost. Future generations of these devices can be designed with less real estate consumed for latch-up suppression (wider spacings, guard rings, etc.), further reducing costs. Because of the unique electrical and materials benefits afforded by buried layer structures, R&D of their integration into mainstream CMOS production is active at leading IC manufacturers worldwide.
References
1. S. Wolf, Silicon Proc. for the VLSI Era, Vol. 2, Lattice Press, 1990, pp. 400-419.
2. W. Morris, et al., "Buried Layer/Connecting Layer High Energy Implantation for Improved CMOS Latch-up," Proc. of the 11th Intl. Conf. on Ion Implantation Technology, Austin TX, June 1996, pp. 796-799.
3. K. C. Leong, et al., "Superior Latch-up Resistance of High Dose, High Energy Implanted p+ Buried Layers," presented at the 12th Intl. Conf. on Ion Implantation Technology, Kyoto, Japan, June 1998.
4. T. Kuroi, et al., "Characteristics of Junction Leakage Current of Buried Layer Formed by High Energy Ion Implantation," Proc. of the 22nd Intl. Conf. on Solid State Dev. and Materials, Aug. 1990, pp. 441-444.
5. K. Tsukamoto, et al., "High Energy Ion Implantation for ULSI: Well Engineering and Gettering," Solid State Technology, June 1992, pp. 49-55.
6. L. Rubin, et al., "High Dose p+ Buried Layers for Reduced Diode Leakage," The 12th Intl. Conf. on Ion Implantation Technology, Kyoto, Japan, June 1998.
7. J. Y. Cheng, et al., "Formation of Extended Defects in Silicon by High Energy Implantation of B and P," J. Appl. Phys., Vol. 80, Aug. 15, 1996, pp. 2105-2112.
8. L. Rubin, et al., unpublished.
9. V.C. Venezia, et al., "Mechanism for the Reduction of Interstitial Supersaturations in MeV-Implanted Silicon," Appl. Phys. Lett., Vol. 74, March 1, 1999, pp. 1299-1301.
10. L. Rubin, et al., "Effective Gettering of Oxygen by High Dose, High Energy Boron Buried Layers," The 12th Intl. Conf. on Ion Implant Tech., June 1998.
11. J. L. Benton, et al., "Iron Gettering Mechanisms in Silicon," J. Appl. Phys., Vol. 80, Sept. 15, 1996, pp. 3275-3284.
12. O. Kononchuk, et al., "Gettering of Fe to Below 1010cm-3 in MeV Self-Implanted Czochralski and Float zone Silicon," Appl. Phys. Lett., Vol. 69, December 30, 1996, pp. 4203-4205.
13. L. Rubin, et al., "Defect Evolution and Metals Gettering by High Dose, Boron Buried Layers," presented at the 12th Intl. Conf. on Ion Implantation Technology, Kyoto, Japan, June 1998.
Leonard Rubin is the chief scientist at Eaton Corp., Semiconductor Equipment Division, 108 Cherry Hill Drive, Beverly, MA 01915; ph 978/232-4266, e-mail [email protected].