Roadmapping Over Shifting Terrain

05/01/1999

ULSI chip production is a very risky affair. Risk comes from trying to control extremely complex processes in a high-volume manufacturing environment. Roadmaps are developed to determine the least risky paths to follow, but the terrain may be starting to shift faster than we can generate accurate maps to extrapolate the Moore's Law trendline.

The number of new materials and processes required to improve chip performance continues to increase, and it can take several years for a radically new process to be developed. IC manufacturers today have to make strategic decisions about what processes they will use several years into the future. In many cases, these decisions have to be made with what can only be described as incomplete data.

It is nearly axiomatic that new enabling technologies (such as low-k dielectrics for interconnects, or post-optical lithography) will cost more than those replaced. Additional costs (and risks) are justified by increased overall manufacturing productivity, but the path to productivity is not necessarily straightforward. In particular, yields can drop precipitously when the simultaneous introduction of too many new processes erodes control.

With gradual death by obsolescence awaiting those who stay in place, chip manufacturers must constantly look for the least risky path to follow among a great many options. Roadmaps reduce overall industry risk by coordinating the development of technologies that will be required.

Moore's Law states that the number of transistors on a chip doubles on a predictable timescale, as a result of design shrinks, larger die, and design efficiency. In addition to the drive to produce more powerful chips, fabs have to increase manufacturing efficiency in the face of intense price pressures. Design shrinks are particularly powerful, as they allow a fab to increase both device performance and manufacturing efficiency (see Industry Insights).

When the move to 300mm wafer processing was delayed by worldwide production overcapacity and equipment cost concerns, fabs aggressively pursued shrinks to improve efficiency. Traditional shrinks along a roadmap were the least risky moves for fabs to pursue, compared to the challenges in moving to either 300mm wafer processing, entirely new chip designs, or radically new materials and processes. As a result, the timescale for shrinks contracted from the historical three years to two years.

Many people in the industry now question how long the two-year rate can be sustained, since there are certain unavoidable physical limitations on building semiconductor ICs. Below 0.18 micron - the process "generation" currently ramping in leading worldwide fabs - the risk and expense of successive shrinks skyrockets. Lacking a dependable roadmap for continued shrinks, companies are looking at other options.

One option is to ignore the roadmap altogether, and to go off-roading. Motorola's announcement of 0.09 micron minimum features without shrinking interconnects or overall chip size is one such option. By shrinking only the active areas, a microprocessor chip can increase its operating speed (within interconnect limits) with only a need to change a few lithography steps. Yield should be high, since only part of the process changes. Cost will be low, and ramp-up should be extremely fast on existing production lines.

In a comparable strategy, TI plans to produce 0.10 micron transistors on its DSPs without necessarily shrinking interconnects or overall chip size. IBM knows that SOI, SiGe, and copper/low-k interconnects can be combined to produce dramatically faster chips without a traditional shrink. Such strategies are "off the map" of our traditional view of shrinks.

In light of these major off-road trailblazers creating new paths to travel, it may be time to reconsider the format and character of our roadmaps. Even more than before, it is clear that a map is needed to negotiate the risky terrain. However, the terrain is becoming so complex that we may soon need a complex topographic map, not a relatively simple 2D plot of discrete streets.