Issue



Technology News


05/01/1999







Novellus drops parylene, bets on SiOC low-k
As a testament to the difficulties in simultaneously meeting technical and business specs for important new processes, Novellus has canceled its parylene low-k dielectric deposition program. Wilbert van den Hoek, Novellus Group VP of dielectrics, stated that the film met all technical specs and worked well in customer demos but required an integration sequence substantially more expensive than competing technologies. A family of competitively priced CVD processes to produce carbon doped glass (SiOC) will be the company's new offering.

Despite several years of effort and the showing of an alpha-tool during Semicon West 98, Novellus determined that its 2.7 k parylene cannot be integrated into a copper dual damascene interconnect structure without costing more than a spin-on dielectric process (with very similar final film properties). Parylene rocessing (including -F, -N, and -AF4 variants) starts with a solid dimer precursor that is sublimated, cracked into monomers in a prereaction chamber, and then vapor condensed/cross-linked on the surface of the wafer.

  • a-CF. Amorphous carbon fluoride
    (a-CF) is one of the more promising CVD materials, with stable 2.3 k reported by researchers from NEC. Endo, et al. disclosed integration details required to produce a 22% reduction in wiring delay, including the need for a post-deposition anneal at 400?C to drive off residual gases in the film prior to oxide capping. A TiN barrier with a 370?C blanket W plug process, and a 350?C Al process combined to show proof of concept for a three-level interconnect suitable for 1Gbit DRAMs.
  • Xerogels. Solgel spin, aging, and bake processes can produce films with some percent porosity to lower the dielectric constant (because gas has 1 k). IBM continues to pursue ethylsilsequioxane- (MSQ or MSSQ) based films, while the Union Chemical Laboratories of ITRI, Hsinchu, Taiwan, are working on porous silica films. Both groups achieve 2.0-2.5 k, though integration work has not yet been disclosed.

  • Parylene. Parylene is a 2.7 k psuedo-crystalline family of materials that requires unique deposition pro cesses. The standard process - used until recently by Novellus (see "Novellus drops parylene," p. 22) - sublimates a solid dimer source; the dimer is cracked into monomers in a high-temperature pre-reaction chamber, and the monomer finally absorbs and polymerizes onto the wafer surface. The Jet Process Corp., New Haven, CT, showed proof-of-concept of a jet vapor deposition (JVD) process using Parylene-N and hydrogen. The resulting amorphous film had 1.9-2.5 k. -E.K.

Fluorine doped SiO2 (SiOF) is a 3.5 k CVD film that is only now starting to be used in volume production, as a stop-gap between 4 k SiO2 and the more desirable but difficult/expensive to process <3 k materials. The current market battle is shaping up between companies offering 2.5-3.0 k technologies.

At CMP-MIC, new models impose science on CMP Though CMP is still far more of an art than a science, numerous researchers are invoking "first-principles" of chemistry and physics to explain and predict what happens when wafer-meets-pad, as attendees at the 4th Chemical-Mechanical Planarization for ULSI Multilevel Interconnection Conference (CMP-MIC) recently learned.


  • Modeling. The largest category of papers at CMP-MIC, held in Santa Clara, CA, dealt with models to explain the complex chemical and mechanical forces that ideally remove only the elevated features on a wafer. One basic aspect of CMP that has recently been resolved is the relationship between pad pressure, relative pad:wafer linear velocity, and planarization efficiency (how little material is removed from recessed features).


   Prior reports had mistakenly associated velocity with efficiency, but researchers at Cybeq Nano Technologies and Philips Semiconductor presented results showing that the efficiency is inversely proportional to pressure. Of course, for a given pressure, increasing velocity increases overall removal rate (and thus tool throughput) while maintaining the same efficiency.

SiOC can be deposited in standard parallel plate PECVD systems, and the "silicone-rubber-like" films reportedly avoid three critical integration challenges:
1. SiOC is not UV absorbing, so an opaque hardmask isn't needed for lithography.
2. The as-deposited film requires no stabilization anneal.
3. Post-etch sidewalls require no stabilization treatment.

Bin Zhao of Conexant Systems (formerly Rockwell Semiconductor) said that a minimum threshold pressure is required to initiate removal in both metals and oxides. Also, researchers at the IBM/Siemens DRAM alliance showed that the W removal rate is inversely proportional to the slurry viscosity.

  • Slurriless pads. The consumables in CMP processing are the single greatest cost of owning a CMP process tool. Also, pad wear combines with particle agglomeration to create process control problems. Embedding the particles, or some form of abrasive structure, into the surface of the pad itself should theoretically reduce process variation and could reduce costs. Presentations from 3M, St. Paul, MN, and Rohm, Kyoto, Japan, showed slurriless proofs-of-concept, and Hyundai presented data showing 3M's pad had much greater planarization efficiency than a traditional slurry system for interlevel oxide CMP.


  • Ta 1:1:1 slurry. Copper is still the hot topic for the industry, as the world moves to catch-up with IBM's damascene process development. The CMP step is critical, particularly the removal of copper barrier layers such as TiN, Ta, or WN. Ta is the preferred barrier material for many reasons, though its removal rate has not been compatible with Cu and oxide. Rodel has now developed a slurry that achieves equal removal rates for Ta, Cu, and oxide to eliminate micro-dishing effects.


  • Ceria slurry. Oxide CMP for hallow trench isolation (STI) requires a slurry that has excellent selectivity to nitride. Ceria-based slurries achieve 100:1 selectivity, but they are susceptible to much more particle agglomeration than silica-based slurries (often causing greater than 10 times more scratches). However, proper slurry management - mostly filtration during process - can bring scratches down to acceptable levels. -E.K.

    Depending on the precursor chosen and the eposition conditions, films can be produced with 2.5-3.0 k that simultaneously demonstrate adequate mechanical stability. The 2.7 k film is not only stable as deposited, it's hydrophobic so it can reportedly withstand room temperature humidity exposure for several days. The CVD process is very similar to that used to deposit standard PECVD oxide: deposition occurs at 400°C, and the company's six station Sequel tool can coat 55 wafers/hour with a 0.5Em film.

    Patent Briefs

    Numerical Technologies,Santa Clara, CA, has received a patent on its double-exposure phase-shift photomask technology, including the algorithm for phase shifting, the software that implements the algorithm, the phase-shifting mask set and the actual use of masks employing this phase shifting approach. The NumeriTech concept uses a dark-field phase-shift mask and a separate binary bright-field trim mask to make a single device layer; this replaces a single high-complexity mask with two simpler ones. The patent was originally filed in 1996 by president/CEO Buno Pati and CTO Yao-Ting Wang.

    The process requires a relatively low-density plasma. A high-density plasma (HDP-CVD) breaks the precursor into its component ions so that some form of SiO or SiC is deposited; thus, the SiOC cannot be deposited in an HDP-CVD tool used for intra-level dielectric gap-fill. For near-term dielectric gap-fill requirements, the company still offers 3.5 k SiOF on the HDP-CVD Speed platform. Novellus has a large team working on SiOC, and expects to field a dual damascene process on the Sequel system this summer. Selective customer demos have already started. -E.K.

    Applied Materials, Santa Clara, CA, and RTP system maker STEAG AST Elektronik GmbH and its subsidiary STEAG AST Elektronik U.S.A. have settled the pending RTP-related patent litigation between them, agreeing to end all suits and set up cross-licensing deals. Terms of the settlement were not disclosed. Under the settlement, Applied agreed not to sue AST on its illuminator patents, and AST said it would not use a discontinued RTP lamp array. Not included in the settlement is the pending litigation between Applied and AG Associates, which has been acquired by STEAG AST.

    Report from DUMIC: Low-k still in development
    It is still too early to call the winners in the race to develop new low-k materials and processes for on-chip interconnect formation. That sobering message was deduced by attendees at the 5th Dielectrics for ULSI Multilevel Interconnection Conference (DUMIC). Process integration of these new materials was the focus of the conference, continuing last year's theme.

    Litho stitching process

    Engineers at Tower Semiconductor have developed a lithography stitching process that extends the resolution of CMOS image sensors (CISs) without necessitating smaller CIS pixels and costly higher resolution lenses in systems that use CISs. This SEM micrograph above shows stitched metal lines. Using i-line steppers, the method is applicable down to 0.3Em features and enables a single CIS to contain millions of pixels; stitched CISs are only limited by wafer size. The significance is that CISs can now compete with older charged coupled device (CCD) technology. Large CIS arrays also will yield substantially better than CCD sensors because, unlike CCDs, CIS pixels are not coupled electrically for sensor operation. While Tower has not revealed details of its patent pending process, some of its success is related to alignment target placement and accuracy. -P.B.

    Much of the debate over low-k technology is between the advocates of CVD and spin-on dielectric (SOD) techniques. Low-k dielectric CVD processes are pushed by the oxide CVD equipment companies as a way to extend product lines with minimal investment. SOD processes are advanced by the materials suppliers, who perceive an opportunity to take market share away from CVD.

    CVD processes can be simpler, with barrier layers deposited in situ, and reduced (or eliminated) need for a post-deposition stabilization anneal. SOD processes can be less expensive and more extendible; the same less expensive equipment can deposit most materials under consideration. Both technologies are transitioning into process integration.


    The fast pace of R&D in the middle of this decade fooled many people into thinking that process integration of these new materials would be similarly rapid. Several years ago, it seemed that low-k ILD layers would replace oxide in most chips before copper replaced aluminum. However, though copper is notoriously difficult to integrate into production, the lack of options forced almost everyone to focus on its development. With far too many low-k options, world resources have been split into many individual development programs.