Issue

Low-k dielectric costs for dual-damascene integration

05/01/1999

Low-k dielectric materials and processes for ULSI
interconnection were sorted to create generic Cu
dual-damascene process flows. Average material and equipment costs were then used as inputs to a generic cost-per-wafer (CPW) model for dielectric deposition (not including the costs of dielectric CMP, metallization, or lithography). Despite being completely different processes, both CVD and spin-on dielectric produce competitively priced films in the 2.3-3.0 k range. The generic model
outputs are useful for comparing specific processes.

Silica-based glasses, with dielectric constant (k) ~4, have been used for decades to isolate the metal lines on ICs; but as circuit speeds rise, the interlevel dielectric (ILD) k directly contributes to circuit delays [1], so a tremendous number of organic and inorganic dielectric materials and processes are under development [2].

Multiple fundamental materials properties are required for ULSI interconnect isolation. Process integration is significant, with trade-offs in cost/complexity between dielectric isolation, metallization, planarization, and lithography. Advantages gained in one area generally result in disadvantages in another, and meaningful comparisons of the suitability of different materials for high-volume ULSI manufacturing are difficult.

For example, one of the main material property trade-offs in dielectrics is that as k is lowered (highly desired to reduce delays in high-speed circuits), the thermal conductivity is also lowered (very undesirable, since high-speed circuits generate heat that must be dissipated). Integration challenges include deposited film stability under O₂ plasma exposure during etch and resist strip, adhesion to copper barrier layers, and thermal stability during metal deposition.

Additional processing, such as the deposition of a capping layer or a stabilizing bake step, adds complexity and cost to complete process realization. Ultimately, integration costs will gate whether a material can even be considered as a candidate for production.

An earlier study compared the suitability of low-k dielectric interconnect materials for ULSI manufacturing, since processes and the materials themselves were still under development [3]. Now, two years later, the immediate need for a modestly lower dielectric for gap-fill between subtractive aluminum lines is well established; there are multiple deposition technologies that can produce 3.0-3.5 k films in a standard aluminum process flow.

Still lower ks are needed, however, for ever-faster chips, and research continues on new materials and processes that can achieve 2.0-2.7 values. At this point, it appears highly unlikely that a k <2 material can be produced that is compatible with high-volume, economical semiconductor manufacturing.

This paper defines generic dielectric deposition technologies within a copper dual-damascene interconnect process, and models correspondingly generic integration costs to aid in the comparison of widely different materials and processes.

Modeling challenges

The relative cost of dielectric formation is only one parameter to be considered in interconnect integration. The costs involved in metallization, planarization, and lithography are equally important, but because the basic dual damascene copper deposition and CMP processes are fairly well established, and because known optical lithography extensions can already be modeled, the cost of low-k dielectric deposition remains the largest unknown. Thus, while only the cost of dielectric formation is considered here, it is hoped that the model outputs can readily aid in comparing costs of overall integration.

define different potentially viable damascene architectures,
catalogue the major families of low-k dielectric materials,
establish commonalities between individual process flows,
identify the processing equipment required for each flow,
obtain average materials and equipment costs,
make extensive assumptions to limit the variables, and
calculate with a modified industry-standard cost-of-ownership model.

The ILD within and between metal lines has generally been CVD SiO₂. Since there was generally a single technique that deposited a single material to surround metal lines, people continue to discuss the ILD as a single layer, sometimes called inter-metal dielectric (IMD). In future device generations, the difficulty in meeting many simultaneously difficult material properties will result in more complex structures. The ILD will no longer have to be a single film or structure. For this study, the intralevel dielectric (IaLD) between lines within a given metal layer (gap-fill in the standard subtractive-metal process) is defined separately from the interlevel dielectric (IeLD) between metal layers.

Materials choices

Despite several years of concerted global development, there are still a wide variety of potential low-k dielectric materials and processes under consideration for ULSI interconnection. With no one obvious choice, development resources are spread thin while investigating multiple options.

For the purposes of this study, general categories of materials were sorted by the process used to produce the thin-film (Table 1).

SiOF - also termed fluoro-silicate glass (FSG) - films can be produced by both plasma-enhanced CVD (PECVD) and high-density plasma CVD (HDP-CVD) systems. Minimal hardware modification is needed to convert a system from SiO2 to SiOF processing. This film, with k = 3.5, can be seen as a relatively easy drop-in for an established oxide gap-fill step in a subtractive aluminum flow. However, by the time fabs migrate to dual-damascene flows, entirely new unit processes will be required and there is little incentive to start over with a not-very-low-k of 3.5. Extendibility to future device requirements is needed to justify an entirely new process, so it is assumed that SiOF will not be used with dual damascene.

SiOC films, though still somewhat new, can be produced in standard PECVD systems. Sometimes called "carbon-doped glass," an SiOC film can be any one of a variety of glassy materials composed of differing or ganic molecules. Precursors vary accordingly. For a given precursor (and perhaps for others with a similar molecular backbone) there is an almost linear correlation between k and film density (Fig. 1). Thus, though the film is essentially single-phase without obvious pores, a "loosening" of the final film structure seems to be the main mechanism for reducing k.

a-CF, also termed fluorinated amorphous carbon (FLAC) or CFx, is the name for a variety of amorphous, highly cross-linked films that can be produced by CVD. Controlling the F/C ratio in the precursor(s) and plasma parameters eliminates the formation of electrically conductive C=C sp2 bonds that otherwise produce leaky films [4]. Multiple barrier and adhesion layers may need to be deposited in situ to isolate the F inside the film.

Despite the wide variety of different spin-on dielectric (SOD) materials, including hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), fluorinated and nonfluorinated poly-arylene ether (PAE), and xerogels (also termed "nanogels" and "nanofoams"), they all use a similar process flow: spin, 2-3 single-wafer solvent evaporation bakes, and a batch furnace cross-linking cure. Thus, though they have different microstructures and material properties, they can all be considered within the same process family.

Xerogels and other SODs with overtly porous structures require tightly controlled molecular cross-linking to produce two-phase films. This step occurs within the solvent evaporation bake series, and chemical and thermal ambient control may necessitate more expensive tooling. Still, it is assumed that this hardware will be physically located inside the spin-on tool with only minimal additional expense.

Parylene, though a potentially useful material, is not considered in this study because data is not yet available from high-volume production tools. Preliminary development implies, however, that deposition and integration costs would be similar to those for a-CF. Other still-novel processes (such as vapor deposition + cure, directly imageable materials, and dip-coating) are currently too difficult to model because baseline numbers are not available. Consequently, they are not considered here.

Process and equipment assumptions

The following generic chip parameters were assumed for 0.18?m devices using 200mm wafers:

400mm2 average chip size (between memory and logic),
0.01 defects/cm2 for each process step, and
5% fault probability (that a defect is a killer) results in 0.2% die yield loss.

Wright Williams & Kelly's TWOCOOL cost-of-ownership software package, commercialized from Sematech and compliant to Semi Standard E35, was used as the basis for calculations. Unless otherwise stated, TWOCOOL default values were used (including administrative rates such as labor and cleanroom area costs).

Defect costs were set to zero for the initial calculations to show the direct CPW, instead of including the cost of lost die sales (which can exceed the direct processing costs for high-price die). The cost of bad die, as the cost to process additional wafer area, can then be added.

The following integration assumptions were required:

To minimize integration problems, fabs will use only one low-k ILD material at a time. Even though trade-offs between thermal-conductivity and k for a given material may make a bi-layer structure desirable for ultimate chip performance, manufacturing costs and process ramp times will favor single-material designs.
Though HDP-CVD systems are used for IaLD in the standard process (gap-fill), less expensive PECVD tools will be used for all damascene CVD.
SOD films will not require an undercoat, since early direct-on-metal results were promising [5, 6], and continued development has shown that spin-on processes can be tuned to prevent delamination and other surface incompatibilities.
Standard (single-phase) SOD films will not require an independent 1000? PECVD cap layer for isolation from moisture and plasma, or for damascene etch definition [2]. Despite initial results indicating otherwise, a barrier will probably not be needed for etch definition with many low-k films; IBM's current dual-damascene process flow does not require a barrier layer to define trenches in SiO2, and sufficient etch uniformity can probably be extended to most low-ks. The lithography and etch processes define line sidewalls, while Cu CMP defines the top surface; thus an etch-stop layer only benefits definition of the bottom of a line. Since the bottom is only 10% of the surface area of a 4:1 aspect-ratio line, physical variation here should have reduced effect on electrical conductivity variation.
a-CF CVD and some SOD films are likely to exhibit chemical instability during subsequent processing, and require a via treatment after etch (whether a thin deposition, a densification, or a plasma treatment). Porous films may need a barrier to cover up the pores that could entrap etch residues, moisture, and outgassing species.

Porous SOD, though perhaps more difficult to control, will be processed with a standard SOD flow. SOD system cost should be slightly higher to process porous films, because of the need for more complex hardware. It is assumed that overall spinner-track throughput will be reduced by 25% compared to a single-phase SOD because of the requirement for more complex thermal treatments.
SOD material costs, in eventual high volume production, will be close to current SOG cost (~$1/g) even though current prices are typically double this. Materials suppliers' fixed costs (and corresponding selling prices) are somewhat independent of the particular chemistry involved.
SOD processing will require that ~2.5 g of liquid precursor be spun onto the surface of a 200mm wafer to achieve a final 1?m film thickness. More efficient linear extrusion and/or meniscus coating techniques (that could theoretically require only 1 g of liquid) have been investigated for several years without encouraging results, so it is assumed that puddle + spread will still be required for final film uniformity.
CVD SiOC deposition rates and equipment costs will equal SiO₂.
a-CF deposition rate will be half of SiO2, with equal tool costs. Some of the reduction in deposition rate can be assigned to the main material, while some is assigned to forming in situ barrier layers for adhesion and chemical protection.

All equipment will meet NTRS defects, availability, etc.
All equipment will be bulkhead-mounted cluster tools, including track systems with integrated single-wafer cure/aging hotplate chambers.
Particles added/pass through any cluster tool are equal.

Equipment and materials suppliers provided data for 1.0?m-thick blanket depositions (and stabilization, if needed) to achieve a total dual-damascene thickness of 2.0?m. This thickness was arbitrarily chosen as a baseline, though most mid-level dual-damascene interconnect structures will be closer to 1.0?m in total. Also, any a-CF under- and overcoats are assumed to be deposited in situ [7] the CVD chamber, and thus do not enter into calculations except as a reduction in throughput. Cap layers were modeled as 0.1?m PECVD layers.

Within ?25%, all 200mm wafer cluster tools (whether CVD or spin-on + bake track) will require 6 m₂ of Class-100 cleanroom area. A rough estimate of $0.50/wafer for bulk gases and equipment consumables was used. The a-CF precursor cost was assumed to be equal to SiOC. The standard SOD throughput assumes that the bakes and cures will not be bottlenecks within the track cluster-tool, while porous SOD throughput will be reduced by 25%. The only remaining variables for an individual layer deposition were tool cost, throughput, and precursor (including in situ NF₃ clean for CVD) material cost (Table 2).

Results

Comparing CVD and SOD costs for an individual deposition, the material costs dominate SOD while the equipment costs clearly dominate CVD processes.

The outputs of the cost model can be summed for each of the generic process flows (Fig. 2). The cost of any via treatment is assumed to be equal to PECVD cap deposition.

There is a clear correlation between the number of processing steps required and the cost of the complete process sequence, regardless of the cost of the individual steps, so CVD or SOD processes that do not require etch-stops or via treatments are always less expensive.

Process flows with additional steps add cost above the sum of the steps. A typical 0.2% die yield loss due to particles adds $5/wafer/step (not counting the cost of lost die sales). Thus, the direct costs will be at least twice that of the simple sums of the individual steps. Also, multitool process flows never reach optimal utilization due to capacity mismatch, so the effective throughput is lowered and costs increase.

Conclusion

Since these results do not include the costs of CMP, metallization, or lithography, relatively less expensive dielectric processes may require more expensive overall processes for complete integration. Also, the less expensive processes tend to have higher dielectric constants, so they may be disqualified by device requirements.

SODs (including xerogels) have nearly equal deposition costs, but overtly-porous materials will require overcoats and additional process steps that significantly increase integration costs. Likewise, CVD materials that do not require overcoats and via-treatments will be strongly favored over those that do.

Lowering k by a certain percentage allows for a corresponding reduction in the number of interconnect layers, and a corresponding cost reduction. Thus, higher processing costs for individual layers are only justified by significantly lower dielectric constants.

As the semiconductor industry approaches the end-game of conventional metal + dielectric interconnects, the processes developed today may well be used for many, many device generations. If the manufacturable k limit is ~2, and a fab already has a 2.5 k process, then a mere 20% improvement cannot be justified unless upgrade costs are minimal. Thus, the most desirable 2.5-3.0 k materials (whether deposited in a CVD or SOD tool) will be those that can be extended to lower k values with the same basic equipment set.

Since the least expensive process (Fig. 2a) is not yet proven, and the most expensive process (Fig. 2d) may be too costly for serious near-term consideration, much of the current contention is between similar-cost CVD and SOD process flows (Figs. 2b, c) that appear to provide very similar final film properties. Fabs with more experience with spin-on glass processing - typically located in Asia - may find SODs to be less risky to develop, while fabs with established multilevel CVD processes may tend to stick with related processes.

Though perhaps over-simple, it is hoped that these relative results are useful in sorting through the wide variety of potential low-k dielectrics for ULSI interconnect isolation. Since the costs for generic processes generated by this model are relatively consistent, similar process flows for specific materials can be compared to these results.

Acknowledgments

Thanks to Dipankar Pramanik (VLSI Technology), Tom Batchelder (Fairchild Technologies), Ashish Asthana (Lam Research) and Alan Levine (Wright Williams & Kelly) for discussion and direction. TWOCOOL is a trademark of Wright Williams & Kelly.

References

T. Seidel, B. Zhao, Materials Res. Soc. Symp. Proc., Vol. 427, pp. 3-16, 1996.
B. Zhao, et al., Materials Res. Soc. Symp. Proc., Vol. 427, pp. 415-426, 1996.
E. Korczynski, Materials Res. Soc. Symp. Proc., Vol. 476, pp. 177-182, 1997.
K.K.S. Lau, C.B. Labelle, K.K. Gleason, Proc. of Dielectrics for ULSI Multilevel Interconnection Conference, pp. 11-21, 1999.
M.K. Jain, et al., Proc. of VLSI Multilevel Interconnection Conference, pp. 23-27, 1996.
V. McGahay, et al., Proc. of VLSI Multilevel Interconnection Conference,
pp. 116-118, 1996.
Y. Matsubara, et al., Technical Digest of International Electron Devices
Meeting, p. 369, 1996.

Ed Korczynski is Senior Technical Editor for Solid State Technology. He received his BS degree in Materials Science and Engineering from the Massachusetts Institute of Technology. He has more than 10 years of engineering and management experience in process development and equipment marketing. His current interests are thin films, process integration, and plasma and vacuum technology. He is a member of the Materials Research Society. Solid State Technology, 1700 S. Winchester Blvd., Suite 210, Campbell, CA ph 408/370-4833, e-mail .