Issue

Barriers for copper interconnections

04/01/1999

The integration of Cu interconnections will require sophisticated structures to prevent Cu from coming into contact with devices. Barrier layers must have good adhesion to both Cu and intermetal dielectrics, and yield desirable microstructure for the deposition of Cu. This paper discusses several critical barrier requirements, and compares the barrier properties of Ta and Ti/TiN layers.

Copper cannot be implemented in the same manner as Al alloys, however. If Cu atoms diffuse into Si devices, they degrade the device performance by introducing deep level acceptors [1]. Typical dielectric materials used in interconnect structures are not effective barriers to Cu diffusion. Also, Cu has poor adhesion to them. Cu interconnect structures, therefore, require complete encapsulation by a thin-film layer that functions as both an adhesion promoter and a diffusion barrier.

The thin-film barrier's surface condition and microstructure can strongly affect the texture and grain size of deposited Cu, critical factors in determining electromigration reliability [2]. Thus, the barrier is vital to seeding the desired Cu microstructure.

In this paper, critical barrier requirements for Cu are discussed, and applied to Ta and Ti/TiN systems. TiN is the most widely used barrier material for Al alloys, while Ta is a promising barrier material for Cu because of its excellent barrier and adhesion properties.

Experiment

Ta or Ti/TiN layers were deposited on thermally grown silicon dioxide (SiO₂) by dc sputtering. Cu films were subsequently deposited by dc sputtering at room temperature. Most Cu films were deposited without a vacuum break following barrier deposition, while some samples were intentionally exposed to air before Cu deposition to examine the effect of in situ deposition on the texture of Cu. A different structure was also fabricated to study the thermal stability of the Ta/Cu interface: a 20-ply alternating multilayer of 13-nm Ta and 18-nm Cu on Si/SiO₂.

The interface between Cu and Ta or TiN layers was observed in cross-sectional TEM and HRTEM (high-resolution TEM) images. During the TEM sample preparation, the samples were kept below 120°C to prevent Cu from oxidizing. The crystallographic orientations of Cu and Ta at the interface were investigated by electron diffraction. X-ray diffraction was used to obtain the global texture of the deposited films.

Results

To prevent the drift or diffusion of Cu atoms, a barrier layer should not react with Cu. The thermal stabilities of various barrier layers with Cu (including TiW, TiN, Ta, TaN, Ta-Si-N and WN_x) are listed in the table on p. 53. Most barrier materials are stable with Cu up to 550?C, and provide adequate thermal stability for current back-end processes. While typical barriers are thermally stable with Cu, other essential aspects need to be considered.

For a given material, there is a trade-off between barrier integrity and adhesion performance with Cu. If the thin-film layer does not react with Cu at all, it may exhibit excellent barrier property but poor adhesion. If the layer reacts too easily with Cu, however, it may not function as a barrier layer despite exhibiting excellent adhesion. For good barrier properties and good adhesion with Cu, an ideal barrier reacts with Cu to some self-limiting extent. In this respect, Ta and TiN layers are investigated and compared.

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Figure 1 shows the cross-sectional HRTEM micrographs at the Ta/Cu interface before and after a 400?C anneal for one hour. Prior to annealing, the as-deposited Cu displays a distinct interface with Ta. However, a 3-nm-thick amorphous layer forms at the Ta/Cu interface after annealing. The mechanism for the amorphous layer formation is not yet clearly understood because Ta has no equilibrium solubility with Cu at 400?C. Nevertheless, we believe that this thin amorphous layer improves the adhesion between Cu and Ta.

We annealed Cu/Ta multilayer structures at various temperatures up to 700°C. Two important observations are noted in cross-sectional TEM micrographs. First, the thickness of the amorphous layer does not increase much with annealing temperature, saturating at about 4 nm. Second, the Ta/Cu interface is stable up to 500°C, but becomes sinuous above 600°C. Furthermore, Cu and Ta grains start to relocate themselves in the course of phase transition from metastable b-Ta to stable bcc Ta. This result implies that the Cu/Ta interface may have good adhesion and be quite stable in the temperature range of typical backend processes (<400°C), and that a minimum thickness of Ta (about 5 nm) is required to allow amorphous layer formation.

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The cross-sectional HRTEM micrographs of TiN/Cu layers are shown in Fig. 2. The TiN/Cu interface has no amorphous layer even after the 400?C anneal for one hour. This absence of interaction should imply potential adhesion problems between Cu and TiN. Indeed, we observed marginal adhesion between TiN and Cu layers during TEM sample preparation, whereas there was no problem between Ta and Cu layers.

Click here to enlarge image

In the HRTEM of as-deposited Ta/Cu (Fig. 1a), the lattice image lines of Cu are parallel to those of Ta. We observed that Ta grains have preferred in-plane and out-of-plane orientations. The [220] direction on a (111) Cu plane is parallel to the [330] direction on a (002) Ta plane, the dominant texture plane of b-Ta [12]. Since a Cu (111) plane has very different symmetry (hexa gonal) from a b-Ta (002) plane (tetragonal), this special orientational relationship is very intriguing. In the projected view of atoms in a Ta unit cell, the (002) plane (at elevation of z/c = 0 or 0.5) exhibits a pseudohexagonal pattern that can be superimposed over the hexagonal Cu (111) plane. The misfit strain at the interface is 7.6% (Fig. 3).

While Ta has a heteroepitaxial relationship with Cu, TiN does not show any special orientational relationship with Cu. As a result, Cu films in situ deposited on Ta have stronger (111) texture than those on TiN under the same condition. There are several reasons why the heteroepitaxial growth of Cu may improve the electromigration reliability of Cu interconnects. First, heteroepitaxial growth may reduce the number of interface defects that can act as void nucleation sites. It may also reduce the diffusion along the interface. Finally, it enhances the (111) texture of Cu, which is known to improve the electromigration lifetime [2].

In situ deposition of Cu on the barrier layer is critical to obtaining strong (111) texture. If the barrier layer is exposed to air prior to Cu deposition, the resulting Cu texture is much weaker than that without air break. This is probably attributable to oxidation of the barrier surface, and the resulting elimination of the pseudohexagonal surface that would otherwise allow for heteroepitaxial deposition.

In addition to the barrier, adhesion, and seed layer properties, there are many other requirements for a good Cu barrier. Since barrier layers increase the resistance of interconnects, layers must be as thin as possible while maintaining barrier properties. The thickness and compositional uniformity of barrier layers must be maintained inside trench structures to guarantee good barrier performance in every location. For better conformality and uniformity, CVD may be preferred over sputtering.

Amorphous materials such as Ta-Si-N typically show good Cu barrier properties under thermal stress because an amorphous layer has no grain boundaries to act as diffusion paths for Cu atoms. However, maintaining uniform composition in the trench is more difficult with amorphous barriers. Also, local crystallization must be prevented.

Since CMP patterns Cu interconnects in damascene process flows, CMP compatibility is a crucial criterion. If the barrier layer can be removed in the same slurry as that used for Cu CMP, the CMP step can be much simpler and cheaper. In this respect, WNx is promising compared to Ta or other barriers, although the adhesion of WNx with Cu must be improved significantly.

Conclusion

A barrier layer for Cu interconnects must satisfy several requirements including barrier, adhesion, and seed layer properties. Both Ta and TiN have good barrier properties. However, Ta has better adhesion and seed properties, due to its heteroepitaxial relationship with Cu and the formation of a thin amorphous layer at the Ta/Cu interface. Even Ta does not, however, satisfy all the other wish list items for barriers, including availability of a CVD process, CMP capability in Cu CMP slurry, and amorphous structure. Further investigation is required to develop the best barrier system for Cu interconnects.

Acknowledgment

This work is partially supported by the Semiconductor Research Corporation under contract IJ-400.

References

R.S. Muller, T.I. Kamins, Device Electronics for Integrated Circuits, 2nd ed., John Wiley & Sons, New York, pp. 1-56, 1986.
C. Ryu, et al., Int. Reliability Phys. Symp., Proc., pp. 201-205, 1997.
S.-Q. Wang, et al., J. of Appl. Phys. 73 (5), 2301-2321, 1993.
J.O. Olowolafe, et al., Appl. Phys. Lett. 58 (5), 469-471, 1991.
D.-H. Kim, et al., Appl. Phys. Lett. 69 (27), 4182-4184, 1996.
H. Ono, T. Nakano, T. Ohta, Appl. Phys. Lett. 64 (12), 1511-1513, 1994.
K. Holloway, et al., J. Appl. Phys. 71 (11), 5433-5443, 1992.
M. Takeyama, et al., J. of Vacuum Science & Tech. B 14 (2), 674-678, 1996.
E. Kolawa, et al., J. of Appl. Phys. 70 (3), 1369-1373, 1991.
T. Oku, et al., VLSI Multilevel Internconnect Conf. Proc., pp. 182-185, 1995.
J. Lu, et al., Adv. Metal.. and Inter. Sys. for ULSI Applic., pp. 87-93, Oct. 1997.
K.-W. Kwon, C. Ryu, R. Sinclair, S.S. Wong, Appl. Phys. Lett. 71 (21), 3069-3071, 1997.

Authors

Changsup Ryu received a PhD in materials science and engineering from Stanford University in 1998. He is now working on interconnect reliability at Motorola Semiconductor Products Sector, Mesa, AZ.

Haebum Lee is working toward his PhD in materials science and engineering at Stanford University.

Kee-Won Kwon is at Stanford University pursuing his PhD in materials science and engineering and an MS in electrical engineering.

Alvin L.S. Loke is an interconnect process engineer at Hewlett-Packard's ULSI Research Laboratory, Palo Alto, CA. He recently received his PhD in electrical engineering from Stanford University.

S. Simon Wong is a professor of electrical engineering at Stanford University, concentrating on interconnect technologies and high frequency modeling of interconnect network, e-mail [email protected].