Fast noncontact diffusion-process monitoring
04/01/1999
Noncontact metrology using surface photovoltage (SPV), contact potential difference (CPD), and corona oxide characterization of semiconductors (COCOS) offers fast, effective control of metals, defect generation, and material properties in semiconductor fabs [1, 2]. We have found its application particularly useful for controlling heavy and alkali metals and dielectric film properties in furnace operations. Here, batch processing virtually dictates fast, tight process control, where just one run can bring economic benefit or disaster to a fab's bottom line.
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These methods are attractive replacements for conventional, more time-consuming, MOS capacitance-voltage (C-V) measurements, significantly reducing costs and increasing overall equipment utilization. The first advantage of these new metrologies is that they can output wafer maps, compared to C-V's sparse point-by-point analysis. The mapped data in Fig. 1 clearly show that more than 80% of single point measurements on the fingerprint-contaminated wafer would still pass a 1011 q/cm2 mobile charge specification. Such mapping provides a visible way to resolve the possible origins of contamination.
Furnace operations monitoring
SPV test wafers, which are processed with product wafers, do not require any special preparation. An array of parameters (see table on next page) is automatically obtained from a user-defined sequence of measurements, significantly more data than that obtained from conventional C-V measurements (i.e., mobile charge, fixed charge, interface trap density, surface doping, and carrier lifetime). In our case, these data are uploaded to a fab charting system.
This level of information has never been available post-process this quickly. All of the parameters in the table are acquired within 3 hr following the completion of oxidation. Dielectric characteristics, such as VFB and Dit, are obtained automatically, requiring no intervention or assumptions about the sample. Furnace area control parameters - such as diffusion length, quantitative iron concentration, surface recombination or other recombination center concentration, and mobile charge density - may be acquired as whole wafer maps composed of 830 to >6000 measurements, done in 10-30 min each.
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SPV metrologies impose minimal requirements on monitor wafers. The important issues are the detection sensitivity of the iron test [3], the uniformity of selected wafer material properties, and the doping level of the starting materials. Figure 2 describes the relationship between iron detection limit and pre-test minority-carrier diffusion length of a monitor wafer. For example, an initial diffusion length value >300 um will provide iron sensitivity in the 109/cm3 range. (The 1997 SIA Roadmap suggests that bulk iron concentration in silicon must be maintained below 3 X 1010/cm3 to avoid yield loss [4] as CMOS generations transition from 0.35- 0.25 um.) Since iron accumulates in silicon, this relationship can also be used to establish incoming quality control for monitor wafers or when they must be removed.
Another consideration for monitor wafers is that SPV depends on the surface space-charge region and the associated surface potential barrier. This dependence imposes restrictions on the wafer-doping level. A p-type resistivity level near 10 W-cm is adequate for SPV and COCOS measurements.
Our use of these methods, as illustrated with the examples below, has enabled us to identify serious process-related contamination and tooling integrity issues quickly and take corrective actions.
Sodium, chlorine, and charge interactions
While many reports have detailed excellent correspondence between traditional measures of iron and SPV measurements, we studied alkali metals. Our intent was to test whether chlorine present in the oxide, and high levels of fixed charge resulting from oxygen presence during cool-down, would have an effect on the repeatability of the measurement or its sensitivity to sodium.
We grew nominal 1000-A oxides according to a factorial design and contaminated them by spin coating, including a 1-min soak and spin dry, with 10 ppba, 1 ppba, and 0 ppba (i.e., ultrapure water) solutions of sodium. We drove the sodium into the oxide using an applied charge and heat. After cleaning, we tested these wafers by the CPD-MC (mobile charge) method [5], conventional C-V bias temperature stress testing, and secondary mass ion spectrometry analysis [6]. We obtained good agreement of the sodium contamination level in the oxide films between all analyses.
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To test the CPD-MC method for repeatability, we measured each contaminated wafer (i.e., three levels of sodium) five times in succession without removing it from the measurement tool. Each data point in Fig. 3 represents the average of 6000 measurements. The largest across-five-cycle variation was obtained for the 0-ppba treated wafer; however, differences here amount to changes in oxide potential of only 10-30 mV. For 1- and 10-ppba contaminated wafers, regardless of oxidation and anneal-pull ambient, measurement results are very consistent. These results suggest that fixed charge and chlorine in the oxide near the SiO2-Si interface, grown under these conditions, do not trap or appreciably change the concentration of sodium drifting in the oxide over the five measurement cycles. Further, the successive application of charge and heat appears to have no effect on the repeatability of the measurement.
Vapor-borne iron contamination
While iron contamination via cleaning chemicals and direct contact with furnace tooling is well documented [7], we found that rust on various stainless steel, fused silica, and O-ring components, which connect the vertical diffusion tube with its loading pedestal, could be transported via vapor within the quartz envelope and chlorine oxidation ambient of a furnace system. Through chemical analysis, we confirmed the presence of iron-containing dendrites and concluded that during the process-check oxidation step, the small percentage of chlorine present reacted with the dendrites. This reaction gave off vapor-borne contamination that drifted against the gas flow to the wafers in the tower more than 1 ft away.
Our identification of the problem outlined above came from a routine process check for iron using SPV. With this check, we monitor the SPV map average and set our "action level" specification to 1 X 1011/cm3. In this particular case, when the iron rose above the action level after a production run, we removed the furnace from production and performed an in situ clean that reduced iron to a passing level. A failure at the next process check led to removal of the tool from production. Nonproduct processing and cleans showed continued failure and prompted us to disassemble the vertical furnace, at which time we identified and documented the rust problem. Our conclusion was that when chlorine is present, iron occurring outside the hot zone of the furnace may be transported to the process zone.
The importance of SPV as a contamination metrology tool in helping us to identify this problem quickly cannot be overemphasized. Today, pro cess systems are increasingly integrated and enclosed like our vertical furnace system. Even though process engineers and operators are present, process zones and any presence of contamination is typically hidden from view. The contamination would have been noted during scheduled maintenance, but associating it with contamination reaching the wafers in the tower would be less likely.
Sodium contamination
We also found CPD-MC mapping a powerful tool for avoiding sodium contamination problems. For example, during the installation and start-up of a new furnace, the centers of our test wafers were uniformly low in sodium. However, at the very edge, the wafers exhibited high levels of sodium. This contamination was traced to a dedicated wafer-notch-finding system used to orient wafers prior to loading them into the furnace. When repaired, the mobile charge parameters recovered to acceptable levels.
In another example, to evaluate candidate gloves used in our wafer fab, we tested them by simply touching a clean oxidized wafer with a gloved and an ungloved hand, driving any sodium into the oxide with applied charge and heat. We found a maximum value of sodium from the glove at 8.1 X 1011/cm2, confirming this with TXRF analysis. Clearly this particular glove would be unacceptable for process tool assembly and repair or for any procedure in which the handled materials would later contact wafers.
Dielectric characterization
Flatband voltage (VFB) is an important parameter associated with furnace processing. In C-V testing, this is the gate voltage at which the capacitance measured equals the calculated value of the flatband capacitance. The calculation of CFB is based on complicated expressions that include approximations of doping level in the silicon, the metal-semiconductor work function difference, and other factors.
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COCOS measures VFB by applying charge to the oxide surface in small quanta until the value of the surface barrier voltage (VSB) is zero. Because this is different than conventional C-V plotting, we compared, by growth condition, boxplots of VFB values obtained using high-frequency metal capacitor measurements and COCOS (Fig. 4, top). The bottom of Fig. 4 shows the high-frequency C-V curves tied to their boxplot representations.
The mean values of the two methods agree well with a positive offset evident for the COCOS VFB results relative to the C-V data. This offset is likely associated with the difference in the effect and level of the work function between the two techniques. Similar to the metal C-V samples, the COCOS measurements of the nitrogen anneal-pull process show that chlorine-containing films have slightly more negative VFB values compared to unchlorinated films. As expected, the values obtained for the O2 anneal-pull films were more negative due to the increased fixed charge at the SiO2-Si interface [8].
Note that although the average value of the COCOS-measured O2 film is not as negative as the C-V average, for these similar films the spread in values is quite large. The spread of VFB values for the C-V case, although large in comparison to the N2 anneal-pull cases, is not as widely distributed as is the COCOS data. All of the capacitors measured by C-V were located on the wafer roughly one third from the wafer edge, left and right of center. None of the C-V data was acquired above or below the mid line of the wafer, whereas for the COCOS-measured wafers of the O2 case, nine sites each were measured, including the center and in all four quadrants of the wafer surface.
These results imply that in the case of an air leak in an oxidation process containing chlorine, such as a gate step, aside from thickness variation, the resulting product would exhibit a large variation in threshold voltage.
COCOS VFB data are also useful to detect furnace environment control problems when thickness variations are small. We found that even though nominal oxide thickness values had not changed appreciably, the percent uniformity level and VFB data together indicated correctly that the tube integrity had been compromised.
Process integration
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Noncontact acquisition of Dit provides a quick, direct measure of process effects, enabling process optimization and control. We measured as-grown 50-? oxides and subjected them to a soft breakdown field stress using uniformly applied charge to mimic a plasma process. We measured the samples again, and gave them a forming-gas anneal and a final measurement (Fig. 5a). The minimum Dit values obtained for the as-grown oxides increased to over
3 ? 1012 q/cm2eV1 following the oxide stress; the post-anneal Dit levels dropped more than an order of magnitude.
Figure 5b shows example Dit spectra of the three film states. We observed a uniform increase in Dit across the range of VS shown following the oxide stress. Note that the forming-gas treatment decreased the relative level of the spectrum at mid range compared to the as-grown and stressed oxides. Further, the anneal produced only slightly higher Dit levels in the surrounding VS ranges than observed in the as-grown film.
Our analysis showed that forming-gas anneal has a stronger effect on traps at VS values near 0.3 V (mid gap) compared to the trap levels in the other regions of the VS range measured. In addition, by using both the minimum Dit values combined with spectral results, we learned that the anneal process was more or less effective depending on different trap energy levels and that the trap recovery to the as-grown levels was nearly complete. An obvious advantage of this new metrology is that further iterations of tests (i.e., changes to anneal conditions or gas mixtures) may be easily performed on the same samples.
Near-surface doping measurement uses SPV to obtain average doping density in the space-charge region near the surface of the wafer. Routine measurements of monitor wafers indicate NA values in the 1 ? 1015 B/cm3 range, in good agreement with supplier data. In thermal processing, this technique is also particularly useful in testing autodoping and cross-contamination effects in furnaces.
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We implanted p-type wafers with boron followed by RTP activation (Fig. 6). Note that NA for the bare wafer resulted in a log-log plot nearly linear vs. dose. NA values for wafers implanted through the screen oxide are lower than the bare wafers for the lowest dose, but are just below or exceed the bare-wafer case as the dose is increased.
The response differences between the bare- and screen-oxide-implanted wafers are interesting and point to a possible interaction between the activation anneal and the screen oxide containing boron. The bare-wafer response, however, suggests that this measurement could be used as an effective monitor for both implant and activation processes.
Conclusion
We have found that sequenced measurements performed on reusable test wafers enable furnace process qualifications, dramatically reducing costs and risk within a few hours compared to the days typically required using electrical device analysis. The same approach has also helped us accelerate process evaluation and optimization efforts.
Acknowledgment
The authors thank colleagues Eric Persson, Bill Russell, Larry Plew, and Cathy Vartuli for their support. This work was partially supported by the Technology in Florida Initiative 1998. SPV, CPD, and COCOS have been commercially integrated in Semiconductor Diagnostics' FAaST instrument set. COCOS is a registered trademark of Semiconductor Diagnostics Inc.
References
- A.M. Hoff, T.C. Esry, K. Nauka, "Monitoring Plasma Damage: A Real-time, Non contact Approach," Solid State Technology, Vol. 7, pp. 139-152, July 1996.
- P. Edelman et al., "Contact Potential Difference Methods for Full Wafer Characterization of Si/SiO2 Interface Defects Induced by Plasma Processing," part of the SPIE Conference on In-Line Characterization Techniques for Performance and Yield Enhancements in Microelectronic Manufacturing II, Santa Clara, CA, September 1998, Proc., SPIE, Vol. 3509, pp. 126-136, 1998.
- J. Lagowski et al., "Iron Detection in the Parts Per Quadrillion Range in Silicon Using Surface Photovoltage and Photo-dissociation of Iron-Boron Pairs," Appl. Phys. Lett., Vol. 63, pp. 3043-3045, 1993.
- W. Henley, L. Jastrzebski, N. Haddad, Mat. Res. Soc. Symp. Proc., Vol. 315, p. 299, 1993.
- P. Edelman et al., "Measurement of the Mobile Ion Concentration in the Oxide Layer of a Semiconductor Wafer," United States Letters Patent, 1998, Patent No. 5,773,989.
- A.M. Hoff, D.K. DeBusk, "Mobile Charge Testing of Sodium Contaminated Thermal Oxides Using Corona Temperature Stressing," presented at Optical Characterization Techniques for High-Performance Microelectronic Manufacturing, October 1997, Austin, TX, Proc., SPIE, Vol. 3215, pp. 26-34, 1997.
- L. Jastrzebski, W. Henley, C. Neuse, "Surface Photovoltage Monitoring of Heavy Metal Contamination in IC Manufacturing," Solid State Technology, Vol. 35, p. 27-36, December 1992.
- B.E. Deal, "The Current Understanding of Charges in the Thermally Oxidized Silicon Structure," J. Electrochem. Soc., Vol. 121, 198C-207C, 1974.
Authors
Damon K. DeBusk has worked in semiconductor manufacturing for more than 19 years at such companies as National Semiconductor and Advanced Micro Devices. He has served as conference chair for SPIE conferences and as a member of the Sematech Wafer Defect Engineering Task Force, and has authored 23 articles and papers. DeBusk is a member of the technical staff in the Integration Technology Group
at Cirent Semiconductor, 9333 South John Young Parkway, Orlando, FL 32819; ph 407/371-6088, fax 407/371-6964, e-mail ordkd@orntsrv103.
micro.lucent.com.
Andrew M. Hoff received his PhD in electrical engineering from Pennsylvania State University. He has 20 years of experience in microelectronics manufacturing. Hoff is an associate professor of electrical engineering and director of the College Metrology Laboratory at University of South Florida, Center for Microelectronics, College of Engineering, 4202 East Fowler Ave., Tampa, FL 33620; ph 813/974-4958, fax 813/974-3610, e-mail [email protected].