Issue



Wafer-level packaging gains momentum


04/01/1999







As the new millennium unfolds, semiconductor manufacturing will see significant adoption of "wafer-level" packaging, assembly, and test operations. Until very recently, the packaging sequences that translated IC input-output (I/O) pads to a usable, standard footprint were, by convention, done on singulated die. Indeed, the demarcation between "wafer form" and "die form" and associated characteristics (e.g., automatable batch processing for the former and labor-intensive manufacturing for the latter) has separated semiconductor manufacturing into its classic "front end" and "back end."

This conventional demarcation is increasingly blurring as IC manufacturers adopt wafer-level packaging, burn-in, and test. When they are applicable, each offers significant productivity improvements and cost reductions. For example, Motorola reportedly was the first to qualify a production wafer-level burn-in process expected to cut conventional IC manufacturing cycle time by up to 25% and direct manufacturing cost by as much as 15% [1]. An example presented later in this article illustrates how savings and yield improvement are achieved by eliminating multiple steps that require handling individual die.

Cost reductions associated with wafer-level packaging result because these new processes use standard semiconductor front-end processing equipment (i.e., deposition, lithography, and etch). In addition, because packaging steps are done at the wafer level, they inherit the faster turnaround time and flexibility to accommodate the die shrink capabilities of wafer processing.

Packaging evolution and definition

In a simple definition, wafer-level packaging is a continuation of the industry evolution toward chip scale packages (CSPs), and greater adoption of flip-chip technology to address constraints of system board size and performance. In the latter half of the 1990s, conventional IC packaging technology has been extended with CSPs. Initially, most of this work used wire or tape automated bonding technologies while processing singulated die. Still using back-end equipment and materials, CSP solutions often resulted in higher than conventional semiconductor manufacturing packaging costs. Any savings with CSP packaging solutions were only seen at the systems level.

The inherent challenge behind the drive to develop wafer-level packaging technology was to provide complete packaging of an IC at the wafer level (e.g., making a CSP while die are still in wafer form, prior to singulation) with no additional fabrication or assembly processing at the die level. As wafer-level packaging has evolved, the definition of a true wafer-level packaging solution (Fig. 1), one that maximizes the cost savings potential of this technology, has been expanded to include packaging that:


  • uses materials and equipment that process all die on the wafer simultaneously for each process step;
  • is not dependent on fabrication of layers off-line, such as flex films, or the individual placement and connection of features;
  • uses masks and other tooling consistent with standard semiconductor processing, thus assuring quick turns on new designs, as well as rapidly adapting to changes such as die shrinks; and
  • eliminates risks of supply issues with a flex film, for example, and the attendant inventory and scrap costs that this incurs during design changes or a product's end of life.

Perhaps the most significant development is that viable wafer-level packaging solutions, due to their direct continuation of wafer-processing technology, finally keep the cost of an IC package a relatively constant percentage of the total IC cost. With standard IC packaging technology, the cost of the package has always become a greater percentage of the total IC cost as a given design is shrunk. In some cases, the cost of individual IC packaging has exceeded the cost of the IC itself.

Wafer-level burn-in

It is also significant that a true wafer-level packaging technology enables development and application of wafer-level burn-in and test strategies, along with their associated gains in productivity. In general, wafer-level burn-in can be developed as a straightforward replacement of the existing test and burn-in process flow. What is more exciting, however, is that this approach to burn-in and test, if properly addressed, can be an enabling technology for a more radical process flow change that provides very significant reductions in cost and increased yields.

Consider, for example, the current process flow for DRAM packaging and testing (Fig. 2a), which includes significant handling of individual die at every step in the process after dicing. Wafer-level processing could be done prior to dicing the wafer but this alone would provide minimal cost-savings advantages.

Significant savings are not achieved until wafer-level burn-in is applied with wafer-level packaging (Fig. 2b), with just the initial wafer probe test and laser repair done prior to building a wafer-level package. In this scenario, provided the wafer can be probed at speed, the final functional test is also completed at the wafer level. Such in situ wafer-level burn-in is estimated to have the ability to complete 80% of the test vectors, thus reducing the number of functional testers required. A significant advantage of doing all processing at the wafer level is the ability to eliminate tape-and-reel process steps, saving $0.07-$0.10/DRAM and reducing cycle time. Vertical or near vertical integration of DRAM production enables picking components from wafers during memory card manufacturing.

To further optimize the process flow, initial wafer probe can be eliminated. In this situation, the wafer-level packaging process leaves DRAM fuse openings uncovered. Once wafer-level burn-in is completed, it is possible to laser repair the burned-in wafers. This can enable a 1-3% improvement in DRAM yield.

This is just one example of the possibilities. But it is important to understand that not all wafer-level packaging technologies permit or enable new process flows and the attendant test and process cost reductions. In most situations, there must be design rule modifications made at the design stage and very close cooperation between packaging and IC design engineering. For the DRAM case, design rule changes are needed to assure there are no fuses under a solder ball or under a redistribution trace. Ideally, the package engineer will provide the wafer-level package design rules to the chip designer and, as part of the IC design, all redistribution routing and ball placement would be completed.

The packaging continuum

The dramatically growing use of wafer-level packages is not a fundamental change in semiconductor assembly and packaging, but rather a significant addition to the continuum of packaging solutions.

First, wafer-level packaging must still conform to standard surface mount technology (SMT) if it is to continue to gain wider acceptance. The standard SMT process flow is stencil-printed solder paste, component placement, and reflow. If a component requires special handling due to the nature of its leads or if vision centering is required, it will not find wide acceptance in the market. Further, components, including those fabricated with wafer-level packaging, must be capable of being placed at a rate of 18,000-20,000 parts/hr. Using a high-speed component placement system, the preferable alignment method is to use only the outline profile of the package. Thus, if the outline of the component is not adequately located relative to the wafer-level package balls or leads, the rate of component placement will be reduced due to the need to locate the balls or leads of the component.

In addition, wafer-level packaging does not in any way supplant the need for an optimized assembly process. Significant work has been done over the past five years in optimizing assembly parameters such as pad size, solder volume, solder mask, or nonsolder-mask-defined pads for ball grid arrays (BGAs), CSPs, and others. This optimization, which includes reliability characterization (see "Wafer-level packaging reliability characterization" on p. 46), must also be done for wafer-level packages, building upon this previous learning.

Using the UltraCSP wafer-level packaging process as an example, two of our most significant findings about assembly optimization have been the type and size of the pad used on boards. As with other CSPs, a nonsolder-mask-defined pad has been found to be optimal. It has also been shown that a smaller pad on the board provides better temperature-cycle reliability.

With proper entry into the continuum of packaging solutions, a wafer-level package is an ideal solution for <100 I/O devices at 0.5-0.8 mm pitch in which all solder balls can fit under the chip. The pitch of the balls, and therefore how many balls will fit under the package, is a function of PC board technology and package reliability objectives.

Even though the technology does not inherently support fan-out solutions, it can fit a wide variety of applications and will ultimately (i.e., within the next five years) be applicable to >25% of all wafers produced. Today's semiconductors that appear to be good candidates for wafer-level packaging include:


  • flash memory;
  • DRAM (64 Mbit and greater);
  • some microcontrollers;
  • integrated passive components; and
  • linear ICs.

A fan-in CSP (i.e., where all the balls fit under the silicon), whether fabricated via wafer-level packaging or conventional singulated processing, is not the ultimate solution for all IC components. For size- and space-constrained applications using a slightly higher 100-200 I/O density chip, it may be more cost-effective to use a flip chip with direct chip attach provided die yield is known. For >150 I/O chips, the most effective IC package is often a wire-bonded or flip-chip IC in a near-CSP or BGA package.

Indeed, appropriate packaging technology will always be a continuum of packaging options that will change over time as board and package technologies continue to advance. Overall system cost will determine the appropriate technology choice. The cost for final product-level assembly is dependent primarily on the routing density required on the board.

Much effort is being spent on moving to micro-via board technology as a way to support the increased routing demands of complex end products. This increased wiring density capability can easily be lost when the required large pad size of a CSP is used vs. the much smaller pad size required for flip-chip components. This becomes especially evident for moderate I/O density IC components (i.e, approximately 100-150 ?m effective peripheral pitch). The data in the table clearly show that peripheral and redistributed flip-chip area arrays can route at least one and in some cases two traces more in the same board space compared to the finest pitch 0.5-mm CSP (Fig. 3).

Conclusion

For the first time, wafer-level packaging technology provides a packaging cost that scales at nearly the same rate as silicon cost reductions. Wafer-level packaging also provides the opportunity for significant cost reductions by rethinking how ICs are designed, packaged, and tested. This is especially true when using wafer-level burn-in and test on the packaged components to dramatically reduce the test cost and potentially improve yield.

Acknowledgment

UltraCSP is a trademark of Flip Chip Technologies.

Reference


  1. "Wafer-level burn-in will cut time and cost," Solid State Technology, p. 20, November 1998.

Author



Peter Elenius received his BS in mechanical engineering and his MS in manufacturing engineering from the University of Wisconsin, Madison. He has managed flip-chip and MCM equipment and process groups at IBM Microelectronics, and was responsible for Kulicke & Soffa's flip-chip equipment program, including the formation of Flip Chip Technologies. Elenius is VP of technology and CTO at Flip Chip Technologies, 3701 E. University Dr., Phoenix, AZ 85034; ph 602/431-6020 ext. 210, fax 602/431-6021, e-mail [email protected].