Advanced wet and dry cleaning coming together for next generation
03/01/1999
Advanced wet and dry cleaning coming together for next generation
Marc Heyns, Paul W. Mertens, IMEC, Leuven, Belgium
Jerzy Ruzyllo, Pennsylvania State University, University Park, Pennsylvania
Maggie Y.M. Lee, Senior Technical Editor, Solid State Technology
Wafer cleaning is the most frequently repeated step in IC manufacturing. Commonly used wet cleaning techniques will remain dominant because of their overall higher cleaning strength. Alternate processes that either reduce or replace chemical usage are being sought because of the current challenges of submicron particle removal, environmental impact from high consumption of water and chemicals, integration into cluster tools, as well as increasing costs. Dry cleaning processes will not replace wet cleans, but will rather complement them and can be used in processes where wet cleans are impractical or inadequate. Wewill discuss here the latest advances in new wet and dry cleaning techniques and the much needed synergy between them for semiconductor processing in the next millennium.
Every wafer processing step is a potential source of contamination, which may lead to defect formation and device failure. Cleaning of wafers must take place after each processing step and before each high-temperature operation (Fig. 1) [1], making it the most frequently repeated step in IC manufacturing. This surface preparation includes cleaning before and after etch, oxidation, deposition, photoresist stripping, and post-CMP residue removal.
Wafer surfaces can have different types of contaminants: particles, organic residues, and inorganic (mostly metal) residues
(Fig. 2). The goal of wafer cleaning is to remove the contaminants and to control the chemically grown ultrathin oxide on the surface.
Most cleaning methods can be loosely categorized as wet or dry. Liquid chemical cleaning processes are generally referred to as wet cleaning. They rely on combinations of solvents, acids, surfactants, and water to spray, scrub, oxidize, etch, and dissolve contaminants from the wafer surface. Thorough rinsing in ultrapure water (UPW) is necessary after use of each chemical. Dry cleaning processes use gas phase chemistry, typically relying on excitation energy to drive the chemical reactions required for wafer cleaning. This extra energy can be thermal, plasma, or radiation. In addition, cleaning can be accomplished by momentum transfer in physical interactions. Dry processes such as in situ Cl-based chemistries [2], Ar sputter, and H2 prebakes have been available for 30 years. While using less chemicals, dry cleaning technologies are not completely free of environmental hazards. For example, waste gases require treatments in wet scrubbers that can generate liquid waste.
 |
Figure 1. Typical process sequence flow [1]
Although there is no single cleaning procedure that is perfect for all process steps, typical wet cleaning sequences contain the following [3]:
Sulphuric acid/hydrogen peroxide/DI water mixture (SPM; H2SO4/H2O2/H2O at 100-130?C). SPM is typically used to remove organic contaminants (often called a "piranha" clean).
Hydrofluoric acid or diluted hydrofluoric acid (HF or DHF at 20-25?C) etch. Removes oxides from areas of interest; etches silicon dioxide and silicon oxides, and reduces surface metals. Buffered oxide etch (BOE or BHF; NH4/F/HF/H2O) is used in place of DHF in some etches but exposure to BHF can lead to NH4F precipitation and contamination.
Ammonium hydroxide/hydrogen peroxide/DI water mixture (APM; NH4OH/H2O2/H2O at 65-80?C). APM oxidizes and slighly etches to undercut and remove particles from the surface; it also removes organic contaminants and removes some metallic contamination. The simultaneous oxidation and etching of the silicon can generate surface roughness.
Hydrochloric acid/hydrogen peroxide/DI water mixture (HPM; HCl/H2O2/H2O at 65-85?C). HPM removes metallic contaminant from the silicon substrate and acts as oxidizing agent.
Ultrapure water (UPW). Commonly called DI water, UPW dilutes chemicals, is used for ozonated water, and rinses solutions from wafers after chemical cleans.
Table 1 lists the most commonly used wet cleaning methods for the removal of each type of contaminant.
The RCA-clean [3], developed in 1965, still forms the basis for most front-end cleans. A typical sequence starts with SPM for heavy organics removal, followed by a dip in diluted HF (DHF). The Standard Clean 1 (SC1) uses APM to remove particles while the Standard Clean 2 (SC2) uses HPM to remove metals. Megasonic energy [4] can enhance this particle removal efficiency, making APM an effective particle-removal solution at room temperature without any significant etching. The compositions (1:1:5 to 1:2:7 for APM; 1:1:6 to 1:2:8 for HPM), and order of the steps can vary but all the wafers are rinsed in UPW after every chemical immersion. The last few years brought many changes, especially in the use of diluted chemistries, but the basic cleaning philosophy used in most fabs is still based on the original RCA-clean.
An important aspect of wet cleaning is the final drying step. Conventional centrifugal spin dryers can leave water marks, induce stress on the wafers, and introduce particle recontamination from static charges. Using a nitrogen ambient at room temperature prevents the formation of water marks but is insufficient to address the other problems. Isopropyl alcohol (IPA) drying requires high temperature and pressure environments, adds to the chemical consumption, and poses an environmental hazard. Commonly used alternatives include Marangoni drying [5, 6] and similar techniques [6] based on surface tension gradients in a thin aqueous film to induce a film of water to flow off the surface, leaving it completely dry.
Advances in wet cleaning
Wet cleaning accounts for an important part of the total fab chemical consumption, and a relatively small improvement in chemical usage has a large overall effect.
The RCA-clean evolved at a time when the scale of the IC industry was much smaller and environmental restrictions were not yet strongly present. Table 2 lists the estimated chemical consumption and values of the bath lifetime in a typical wafer wet cleaning bench [7]. In view of the large volume of water and chemicals used, an optimization of wet cleaning steps is urgently needed.
The new technologies environment-friendly manufacturing emphasize the three Rs - reduce, recycle, and replace - which translate into reduced chemical use, recycling of water, development of alternative
eplacement chemistries, and development of improved dry processing techniques to assist wet cleaning. Mechanical cleaning techniques such as centrifugal spraying [6], water jet, brush scrubbing [6], pressurized fluids, cryogenic particle jets [8, 9], and microcluster beam impact [6] can supplement conventional RCA cleans and cut down on the chemicals and rinse water required.
Recent improvements in wet cleaning have been very successful in reducing costs, chemical and water usage, and required cleanroom space. The number of cleaning and rinsing steps has decreased. For example, Marangoni-based techniques combine the rinsing and drying steps, and diluted chemistries considerably cut down the rinsing required. Many advances are based on the use of diluted chemistries and ozonated UPW as replacements for hydrogen peroxide, or even sulphuric-based mixtures.
 |
Figure 2. Contamination on a silicon surface.
 |
Table 1. Most commonly used wet cleaning methods
Diluted chemistries. Depending on the initial cleanliness of the wafers, diluted APM SC2 mixtures (1:1:50) can sufficiently remove particles and hydrocarbon residues from wafer surfaces. Studies have shown that strongly diluted HPM mixtures (1:1:60) and dilute HCl (1:100) are as effective at removing metals as the standard SC2 solution [10]. The diluted RCA cleans have shown up to 5-6 ? reduction in total volume of chemicals consumed [11]. The implementation of megasonics agitation, diluted SC1, SC2 and HF, reduced bath temperatures, and optimized times of various cleaning steps have led to longer bath lifetimes and a 4-50 ? reduction in consumption. Using warm instead of cold UPW in some instances led to a 3-4? reduction in UPW consumption [7]. Moreover, the much-diluted chemicals allow major savings in rinse water due to the lower flow rates and/or rinse times required. Based on the success of diluted chemistries, IMEC launched a much simpler "Just-Clean-Enough" cleaning approach [12].
Ozonated and diluted chemistries for simplified cleaning. To lower further the chemical consumption during wet wafer cleaning and to offer high cleaning performance at lower costs and smaller cleanroom footprint [13], IMEC introduced a simplified cleaning process called IMEC-clean. It is a simple two step process, with an optional third step before drying [13]. The first step uses a sulphuric acid/ozone mixture (SOM) to remove organic contamination and grow a thin chemical oxide. Under the correct conditions, ozonated UPW (O3/H2O) can replace SOM to reduce chemical consumption and UPW consumption further. The SOM step replaces the standard SPM step, increasing the bath lifetime with a factor of 3. The ozonated UPW mixture alternative completely avoids the use of H2SO4 (in either SPM or SOM) and UPW in the difficult rinse step after the acid bath. The second step uses an optimized diluted HF/HCl mixture to remove particles, metal contamination, and chemical oxide, and to avoid HF-baths [13].
Ideally, a good drying technique for mixed hydrophobic/hydrophilic surfaces should not generate drying spots. For example, with the Marangoni dryer no further surface treatment is necessary. In case a hydrophilic surface is preferred, a third step can be added to regrow a thin passivating oxide layer. Hydrophilic surfaces are typically easier to handle without particle recontamination. Optimized ozonated mixtures, such as DHCl/O3, make the silicon surface hydrophilic at low pH values to avoid the reintroduction of metal contamination. The last rinsing step strongly determines the final surface contamination level, particularly for Ca, which depends on the pH level and cleaning step prior to the rinse [12]. This is especially important since Ca severely degrades the gate oxide integrity.
Typical results for the IMEC clean show very low levels of metal concentration (<1010 atoms/cm2) when ppb-grade chemicals are used. The results also show that the particle removal efficiency depends on the equivalent amount of oxide etched and is comparable to the etching in typical RCA heated SC1 solutions [14].
Figure 3 shows a suggested roadmap to evolve from the standard RCA-clean toward more advanced cleaning strategies with lower chemical and DI-water consumption.
Aqueous ozone reactions. Ozonated chemistries have also shown success in removing photoresist and organic post-etch residues. Boundary-layer-controlled ozone processing, reported earlier [15], enhances the ozone oxidation of the carbon chain in resists and post-etch polymer residues, successfully competing with sulphuric-based stripping procedures and reducing chemical consumption.
Researchers in Japan have reported successful removal of particulate, organic, and metallic contaminants by single-wafer spin cleaning with repetitive use of ozonated UPW and DHF [11]. Similar approaches include a double sequence of O3/UPW and HF steps with the addition of surfactants and dissolved gases [16].
Next-generation technology challenges cleaning
Challenges for currently used cleaning techniques include the need for continued performance improvement in submicron particle removal, environmental impact from the considerable water/chemical consumption and chemical wastes, drying difficulties, and impact on production cost.
Shrinking device geometries and continuously decreasing gate oxide thickness are also imposing more and more stringent sur face preparation and cleanliness requirements.
 |
Table 2. Estimated chemical consumption (liters)
 |
Figure 3. A suggested roadmap for the evolution from the standard RCA-clean toward more advanced cleaning strategies with lower chemical and DI-water consumption.
Some manufacturers are already moving from the production of batch wet cleaning tools to clustered single wafer cleaning, with applications in a polydeposition cluster [17]. Wet cleaning methods are not easily integrated in present tools, which combine several gas phase processes. Thus the availability of dry cleans that could supplement or replace wet surface treatments in specific applications will also play a major part in the success of the transition to =300-mm technology.
Dry cleaning complements wet cleaning
The introduction of dry cleaning technology into advanced IC manufacturing has proceeded at a slower pace than originally anticipated [8]. With wet chemistries meeting most cleaning demands, the introduction of dry cleans depends on a thorough consideration of both advantages and shortcomings in specific applications. Dry surface treatments will increasingly be performing surface "conditioning" functions rather than strictly defined surface "cleaning" functions. Also, dry surface treatments will be implemented primarily in cluster tools rather than in stand-alone tool configurations. The throughput of gas phase cleaning modules in the cluster is likely to be among decisive factors for their acceptance. Ultimately, the cost benefits either through increased yield or decreased cost of ownership will decide the extent of the use of dry cleans in selected applications.
Table 3 lists common methods for the removal of each type of contaminant in the gas phase. Only some of them can be implemented in situ using tools designed to perform other functions. For example, anneal in Cl containing ambients is typically performed in the oxidation furnace as a part of the thermal oxidation procedures. Also, Ar sputtering is commonly carried out in situ immediately before sputter deposition. Other operations would require designated gas-phase processing modules designed for specific operations.
The effectiveness of gas phase cleans is not the same for all types of surface contaminants. Removal of particles remains the greatest challenge. The methods in Table 3 show good promise, but do not currently offer adequate removal efficiency for very small particles. There is also a question of whether dry cleans will meet the critical metal contamination level requirements (<1010 atoms/cm2) for next-generation technologies. Experimental evidence suggests that reducing surface metallic contaminants to this level may not be possible without roughening the surface if metals are present in initial concentrations over 1012 atoms/cm2. This is because most of the gas-phase chemistries cannot selectively interact with surface metallic contaminants without reacting with silicon at the same time. These interactions may actually improve the quality of the silicon surface, but only if implemented under mild conditions in terms of temperature and length of treatment, which may not be enough to remove gross metal contamination [19]. Moreover, the different vapor pressures of volatile compounds of various metals means not all metals can be equally and effectively volatilized at low temperatures. Among the most common metallic contaminants in silicon processing, Fe, Al, Cu, Zn, and Ni can be reduced using gas phase chemistries to the required levels. On the other hand, volatilization of Ca at low temperature (<200?C) has yet to be proven effective using Cl-based chemistries [20].
In contrast to particles, and to some extent metals, volatilization of residual organic contaminants takes place readily by exposing the surface to an oxidizing ambient. Etching of native/chemical oxide is also easily achieved. Among the methods listed in Table 3, processes using anhydrous HF- (AHF-) based chemistries can be implemented relatively easily. Either water vapor or more volatile solvents can initiate the etch reaction. In the first case, precipitation of the etch products on the surface calls for an additional water rinse. In the latter, a high vapor pressure of the etch initiator, such as methanol, will prevent formation of solid residue. The oxide etch rates depend on the type of alcoholic solvent as well as process temperature and pressure used [21].
Application-specific cleans
Chemical cleanliness of the silicon surface is most critical before additive processes because the contaminants can irreversibly damage interfaces as well as deposited materials. The effect of various contaminants, however, is not the same in all deposition processes. Different gas phase cleaning schemes are thus appropriate for different applications. Examples of possible approaches are:
Pre-epi gas phase treatments. To achieve an oxide- and organics-free surface at the onset of epitaxial deposition, it is best to carry out native oxide etching in situ (e.g., H2 anneal) or integrate the surface preparation module with an epitaxial reactor. The trend toward decreasing the temperature of epi deposition below 900?C renders in situ hydrogen reduction of the native/chemical oxide ineffective. Alternative gas phase techniques such as remote H2 plasma treatment [22] and AHF/methanol oxide etch, followed by UV/Cl2 treatment at a temperature below 200?C [23, 24] integrated with an epi reactor, have shown very promising results. Table 4 demonstrates superior cleanliness of the epi/substrate interface in the case when the AHF/methanol oxide etch and UV/Cl2 treatment combination is used prior to 800?C epi deposition without any pre-anneal. The UV/Cl2 exposure slightly etches the silicon surface [9] and in the process, carries away complexes such as Si-O and Si-F, as well as metal chlorides. Remarkably, Cl itself does not remain on the surface. As in the highly volatile Si-Cl configuration, it acts as a "carrier" to lift other complexes off the surface. These treatments assume that prior to loading into the epi cluster, wafers are wet cleaned to remove particles. Hence, the gas-phase treatment applied in a cluster prior to epitaxial deposition is basically a surface conditioning step in which oxygen surface termination following hydrocarbon desorption is not replaced with other termination.
Pre-metal gas phase treatments. Removal of organic contaminants and native oxide are key surface treatments before contact metallization. Metal depositions are primarily back-end-of-line processes that follow dry etching. Hence, pre-metal deposition dry surface processing may consist only of organic contaminants volatilization and chemical oxide etching, or it may be a sequence of post-RIE/pre-metal surface conditioning steps that include slight etching of the Si surface to remove damage [25]. Gas phase processing of the bottoms of contact holes and vias in the case of structures with very high aspect ratios remains an open question.
Pre-gate oxidation. The growth of gate oxides for Si MOSFETS is the single most demanding thermal oxidation process where surface cleanliness is concerned. Various liquid-phase wet cleans are likely to perform adequately down to the thinnest SiO2 gate oxides (~1.5 nm) feasible. Those cleaning techniques are commonly enhanced by in situ anneals in Cl-based chemistries [2]. Hence, from a performance point of view, there may be no reason to search for new dry pre-gate oxidation surface treatments. The transition to single-wafer processing and the search for high-k dielectrics may call, however, for the alternative dry Si surface treatments prior to gate dielectric formation. The entirely dry remote plasma processes [26] as well as a sequence involving a combination of UV/O2, AHF/methanol, and UV/Cl2 steps preceded by wet treatments [20, 27, 28], have shown adequate gate oxide integrity, particularly in terms of charge-to-breakdown (Qbd), of 13-100 ?-thick oxides. Figure 4 illustrates this trend in the case of 3.2-nm gate oxides. Still, gas-phase surface processing prior to gate oxidation requires further research to gain an exact understanding of the correlation between integrity of ultrathin oxides and the chemistry of dry-cleaned surfaces.
Semiconductor companies are also considering other dry clean ing techniques. Specifically, laser cleaning [2, 29], and carbon dioxide snow jet cleaning [2, 30] continue to be explored for particle removal application. In the area of metal volatilization, investigations continue on an approach using metalorganics instead of halogen-based chemistries [31]. Moreover, a remote plasma H2 process for native oxide etching remains a viable option.
 |
Table 3. Commonly used dry cleaning methods
 |
Figure 4. In spite of inferior cleaning strength of gas phase chemistries, gate oxides grown on dry cleaned surfaces (750?C, 3.2 nm) display excellent Qbd characteristics.
 |
Table 4. Concentration of selected elements at epi/substrate interface for wet ex situ and dry integrated surface treatments*
Hybrid cleans may be the answer
The industry should not view dry cleaning as an isolated step, but as a part of the overall surface preparation procedure, taking advantage of both wet and dry chemistries. The dry treatments will benefit the process most if applied as an integrated last operation before the subsequent process step. It will most likely take place in combination with preceding wet cleaning steps that would effectively lead to a broader use of "hybrid" wet-dry sequences. In the hybrid systems, gas-phase chemistries would primarily play a surface conditioning role while wet chemistries would play the cleaning role, particularly for the removal of particles and gross metallic contamination. Obviously, such an approach will only make sense if it leads to gains in performance and/or cost benefits over existing methods.n
Acknowledgments
IMEC-clean is a registered trademark of IMEC. Jerzy Ruzyllo would like to acknowledge past support of dry cleaning research at Penn State by the Semiconductor Research Corp. and Submicron Systems/Primaxx Corp. He would also like to thank IMEC for the support during his sabbatical leave in 1997.
References
1. T. Hattori, in Cleaning Technology in Semiconductor Device Manufacturing V, J. Ruzyllo, R. Novak, Eds., The Electrochem. Soc. Proc., Vol. 97-35, p. 1, 1998.
2. P. W. Mertens, et al., Materials Reliability in Microelectronics VII, of Mat Res Soc Proc., Vol. 473, p. 149, 1997.
3. W. Kern, D. Poutinen, RCA Rev., Vol. 31, p. 187, 1970.
4. S. Schwartzman, A. Mayer, RCA Rev., Vol. 46, p. 81, 1985.
5. A.F.M. Leenaars, J.A.M. Huethorst, J.J. van Oekel, Langmuir, Vol. 6, pp. 1701-1703, 1990.
6. Information on recent related SST articles can be obtained from our sebsite: http://www.solid-state.com/sst/99issue/.
7. IMEC Newsletter, Leuven, Belgium, No. 23, November 1998.
8. W.T. McDormott et al., Microcontamination, Vol. 9, p. 33, October 1991.
9. T. Ito, R. Sugino, Proc. UCPSS `98, Oostende, Belgium, p. 219, 1998.
10. T.Q. Hurd, P.W. Mertens, L.H. Hall, M.M. Heyns, Proc. UCPSS `94, Acco Leuven, p. 41, 1994.
11. T. Hattori, et al., J. Electrochem. Soc., Vol. 145, No. 9, 1998.
12. P.W. Mertens, et al., Silicon Materials Science and Technology, H.R. Huff, H. Tsuya, U. G?sele, Eds, The Electrochem Soc Pro Series; PV98-1, p. 592, 1998.
13. M. M. Heyns, et al., Technical Digest, IEEE IEDM, p. 325, 1998.
14. M.M. Heyns, Proc. Intl. Conf. SEMICON Europa `98, Geneva, Switzerland.
15. S. De Gendt, J. Wauters, M. Heyns, Solid State Technology, Vol. 41, No. 12, p. 57, December 1998.
16. H. Kanetaka, et al., Proc. UCPSS `98, Oostende, Belgium, p. 46, 1998.
17. K. Tsugane, H. Tomioka, K. Shinbara, A. Izumi, Proc. IEEE ISSM `97, San Francisco, p. B-13, 1997.
18. J. Ruzyllo, Proc. Symp. on Contamination-Free Manufacturing, SEMICON West 1998, S. Krishnan and A. Busnaina, Eds., 1998.
19. J. Sapjeta, et al., Proc. Symp. Sci. and Tech. of Semiconductor Surface Preparation, Mat. Res. Soc. Proc., Vol. 477, p. 221, 1997.
20. J. Ruzyllo, et al., Proc. UCPSS`98, Oostende, Belgium, Sept, 21-23, 1998.
21. K. Torek, et al., J .Electrochem. Soc., 142, 1322, 1995.
22. H. K. Yuh, J. W. Park, K. H. Hwang, E. Yoon, and K. W. Whang, in Cleaning Technol. in Semicon. Dev. Manufacturing V., J. Ruzyllo and R. Novak, Eds., The Electrochemical Society Proceedings, Vol. 97-35, p. 307, 1998.
23. J. Ruzyllo et al., Proc. UCPSS`98, Oostende, Belgium, Sept, 21-23, 1998.
24. M. Caymax, et al., Proc. UCPSS`98, Oostende, Belgium, Sept, 21-23, 1998.
25. D.K. Hwang, K. Torek, and J. Ruzyllo, Proc. First Intern. Symp. on Plasma Process Induced Damage, K.P. Cheung, M. Nakamura, C.T. Gabriel, Eds., Am. Vac. Soc./IEEE, p.137, 1996.
26. J. Ruzyllo, D. Frystak, R. A. Bowling, Technical Digest, IEEE IEDM, p. 409, 1990.
27. K. Torek, Ph.D. Thesis, Penn State University, 1995.
28. Y. Ma, et al., J. Electrochem. Soc., 142, L217, 1995.
29. G. Vereecke, E. Rohr, and M. M. Heyns, Proc. IEST 98, p. 202, 1998.
30. E. Westkamper, A. Schule, and D. Werner, Proc. IEST 98, p. 198, 1998.
31. S. E. Beck, et al., in Cleaning Technol. in Semicon. Dev. Manufacturing, J. Ruzyllo and R. Novak, Eds., The Electrochem. Soc. Proc. Vol. 94-7, p. 253, 1994.
Contact Marc Heynes, IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium; e-mail [email protected].