Air gaps lower k of interconnect dielectrics
02/01/1999
Air gaps lower k of interconnect dielectrics
Ben Shieh, Krishna Saraswat, Mike Deal, Jim McVittie, Stanford University, Stanford, California
Established CVD oxide processes can be fine-tuned toproduce air gaps between metal lines to lower the k of interconnect dielectric stacks. Design constraints and integration challenges exist, but air gaps may be easier to integrate than completely new low-k materials. Manufacturable processes can reduce interconnect capacitance by as much as 40-50% for tightly spaced metal lines.
As IC technology scales, the performance of ULSI chips is increasingly limited by the capacitance of the currently used intermetal dielectric: SiO2 [1]. The capacitance of the interconnect dielectric influences the chip speed (RC delay), AC power (CV2f), and crosstalk. A great deal of development is being done on new materials and fabrication technologies to reduce the interconnect capacitance. Current low-k dielectrics under investigation include fluorinated SiO2, amorphous carbon-fluoride, aerogels, and polymers. Using air or vacuum as the only dielectric has also been explored [2].
Unfortunately, the new low-k materials under investigation pose many challenges of reliability, manufacturability, and integration. Some of these issues include: 1) mechanical strength, 2) dimensional stability, 3) thermal stability, 4) ease of pattern and etch, 5) thermal conductivity, 6) CMP compatibility, and 7) complexity of integration. Most low-k materials currently being researched are inferior to SiO2 in most if not all of the above properties [3].
Additionally, as ICs continue to scale, the aspect ratio of metal lines increases so that the intralevel dielectric (IaLD) capacitance increasingly dominates the interlevel dielectric (IeLD) capacitance in determining total interconnect performance (Fig. 1). Thus it becomes increasingly important to implement low-k schemes between tightly spaced metal lines and less so between metal levels [3].
Air gaps formed between metal lines during SiO2 deposition address many of the concerns associated with low-k materials while offering comparable if not better capacitance reduction [4-7]. Air gaps reduce the dominating IaLD capacitance, while leaving the IeLD SiO2 intact to maintain the structural integrity of the interconnect stack. Additionally, since no new materials are introduced, new etch and CMP recipes are not needed and thermal stability is not an issue. Air gaps do, however, present a number of integration and reliability issues that must be addressed before introduction to manufacturing.
Electrical performance
Capacitance simulations. We used a rectangular "box" air-gap geometry to simulate how capacitance reduction varies with air-gap dimensions [4]; the metal height was 0.7 ?m and the IeLD thickness was 0.9 ?m. A relative dielectric constant of 4.1 (typical of deposited SiO2) was used for both the IaLD and IeLD material. The effective dielectric constant, keff, was calculated by dividing the simulated capacitance of the total geometry by the simulated capacitance of the metal geometry in vacuum (k = 1). The calculated keff values are comparable to, or better than, most of the homogeneous low-k materials currently being investigated.
 |
Figure 1. As IC technology scales, the aspect ratio of metal lines increases so that the intralevel line-to-line capacitance increasingly dominates the interlevel capacitance [3].
Although the "box" may not be a realistic air-gap shape, simulations using this shape can assist in determining the important air-gap dimensions affecting capacitance. Simulations become particularly important when deciding how to tailor the air-gap shape to balance the tradeoffs between capacitance reduction and reliability.
Modeling of air-gap technology can be extended from the simple box capacitance models to simulating the deposition used to form air gaps in real-world structures. We simulated a typical air-gap profile with SPEEDIE (Stanford Profile Emulator for Etching and Deposition in IC Engineering). This profile can then be input to an electrical simulator to model the capacitance.
Simulations can predict the capacitance of arbitrarily spaced lines. For example, after obtaining experimental data for the IaLD air-gap structural capacitance between 0.3 and 0.4 ?m spaced lines, SPEEDIE can simulate the deposition and extrapolate what the capacitance might be on wider-spaced lines.
Experimental results. Figure 2 shows a SEM image of air-gap structures processed in a collaboration between Texas Instruments and Stanford University [4]. The air gaps shown were fabricated in a 0.3/0.3-?m line/space array using an HDP-CVD process. Figure 3a shows the electrical data measured on single level metal comb structures with air gaps fabricated using this process. The electrical data for comb structures with HDP-CVD SiO2 gap-filling the space between metal lines is also shown for comparison. Assuming the gap-fill oxide has a relative k of 4.1, the median keff for the air-gap structures is approximately 2.47, a 40% reduction in capacitance.
Figure 3a also demonstrates the uniformity of the process. As the cumulative probability plot shows, the distribution of the air-gap capacitance data is similar to - if not better than - the distribution of the HDP-CVD oxide gap-fill capacitance data. Additionally, there is no significant difference in current leakage data between the air gap and HDP-CVD oxide samples.
Figure 4a shows a SEM image of air-gap structures fabricated at Matsushita [5]. In this process, an over-etch into the oxide layer extends the air gaps below the metal lines, and ensures that no oxide is deposited between the metal lines. As the box simulations predict, extending the air gap above and below the metal lines can be quite effective in reducing capacitance. The capacitance data for these air-gap structures is shown in Fig. 4b.
Process integration and reliability
Unlike most low-k interconnect schemes currently being researched, the use of air gaps does not introduce any new or exotic materials to the process flow. Consequently, no new etch or CMP recipes are required, and process temperatures do not need to be reduced (as is the case for relatively thermally unstable polymers). Air-gap integration issues center on physical compromise of the air gap during subsequent processing, such as in CMP and via formation.
If air gaps extend significantly above the metal lines, then they may be opened during subsequent CMP. Even if the CMP does not remove enough SiO2 to reach an air gap directly, the normal and shear forces during CMP may create enough stress to compromise the interconnect structure.
To ensure that the air gap is not opened during subsequent processing requires that the deposition process be engineered to control the extent of the void above the metal lines. When engineering the process, it is important to consider the deposition topography within and above varying line spaces. A problem with nonconformal depositions is that, while an air gap may form nicely between tightly spaced lines, an air gap formed between wider-spaced lines during the same deposition will be positioned significantly higher relative to the metal lines. There is also the possibility of forming a low quality "seam" that continues through the deposition even after the air gap has pinched off.
One process flow developed at Sandia National Labs solves the problem of forming air gaps in the varying spaces between intralevel metal lines without requiring an additional masking step [6]. The SiO2 deposition is stopped after air gaps are formed between the smallest spaces. A low-k spin-on dielectric (SOD) then fills the re-entrant features in wider spacings that have not yet pinched off. An oxide deposition finally caps the SOD to provide a uniform material surface for CMP. The disadvantage of this process is that it introduces a low-k spin-on material that must be etched through during via definition.
The air-gaps fabricated at Matsushita (Fig. 4a) were shaped by a two-step process (Fig. 5) [5]. A conventional PECVD SiO2 process forms the initial air gap. Then, an HDP-CVD gap-fill process prevents air gaps in the wider metal spacings from extending too far above the metal lines. The HDP-CVD step fills the wider spacings between metal lines, but the sealed off air gaps in the smaller spacings remain.
 |
Figure 2. SEM of air-gap structures in an array of 0.3-?m lines and spaces. The "I-beaming" of the metal lines is an artifact of the cleave.
True metal profiles exhibit only a slight taper.
 |
Figure 3. Electrical data for comb structures with air gaps fabricated at Texas Instruments. Air-gap split a) shows 40% reduction in capacitance, and b) does not show appreciable leakage [4].
We used a similar two-step approach to fabricate the air-gap structures in the Texas Instruments/Stanford work. However, instead of using a PECVD process in a conventional chamber, we developed a PECVD-like process (high gas flow and low substrate bias) for a HDP-CVD chamber to form the air gaps. After some time to allow the air gaps to form, the gas flows to the chamber were decreased and the substrate bias increased, switching to an HDP-CVD gap-fill process that fills the wider spaces. The high sputter component of the second step also prevents a seam from forming above the smaller spaces. This process improves throughput and allows the use of a single process chamber instead of two. In all three of the processes discussed, the experimental air gaps fabricated withstood subsequent CMP.
Another process integration concern is that a slight misalignment during via lithography may result in the air gap`s opening during via etch. Again, control of the air-gap shape and size may be critical to address this issue, especially as technology moves toward zero overlap vias. The process developed at Matsushita gets around this problem by fabricating the vias before the air gap (Fig. 5). In this process, vias are formed above the unpatterned blanket metal layer. Once the vias are formed, the SiO2 ILD and metal are etched using the same mask step. The SiO2 deposition to form the air gaps then follows.
A future concern for air-gap structures is that of integration with metal damascene processes. This will become an important issue with the move from aluminum to copper wiring. With damascene metal processes, integration of air gaps becomes slightly more complicated but can be accomplished without additional masking steps. A process for incorporating air-gap structures with damascene metal is being developed at Stanford; the details will be presented in future publications.
Thermal reliability. Because air or vacuum has such poorthermal conductivity, one must assess the thermal performance of interconnect stacks incorporating air gaps. Increased temperatures in the interconnect stack due to Joule heating can result in many reliability problems, including enhanced electromigration.
The table on page 57 summarizes the simulation results of a five-metal-layer interconnect geometry with different dielectric configurations [7]. The simulation geometry consisted of arrays of aluminum metal lines at each level with a pitch of 0.72 ?m. Each metal layer was 0.8-?m thick, and each IeLD layer was1.0-?m thick. For all simulations, a current density of 0.5 mA/cm2 was used in simulating Joule heating. The silicon substrate at the bottom of the stack was assumed to be the only heat sink in the system. As the table shows, the temperature rise in the air-gap interconnect system is only minimally higher than the homogeneous SiO2 case. In contrast, the interconnects utilizing homogeneous low-k materials may exhibit prohibitively high temperature rises.
 |
Figure 4. Air-gap structures fabricated at Matsushita: a) SEM, and b) electrical data [5].
 |
Figure 5. Process flow for Matsushita-made air gaps [5]; a) via plug formation; b) resist patterning of first interconnect; c) first interconnect formation; d) intermetal dielectric deposition; e) second interconnect formation.
The results can be modeled by a thermal resistance circuit. In each metal layer, the vertical thermal conductivity is dominated by the metal leads and not by the intralevel dielectric between them - whether it be SiO2, low-k material, or vacuum. Between metal layers, however, the thermal conductivity is limited by the IeLD material. In the case of air gaps, the IeLD material is still SiO2, which has a thermal conductivity an order of magnitude higher than typical polymers. It has been shown that the presence of vias does not significantly help heat conduction through the IeLD layers [8].
 |
Electromigration reliability. Another concern with the use of air gaps in interconnect structures is that there may be increased likelihood of metal extrusions, because the sidewall SiO2 passivation is very thin on closely spaced interconnects. To address this concern, the interconnect group at Stanford developed a modeling strategy to assess the tradeoffs between reliability and performance in interconnects using air gaps [9]. In these simulations, SPEEDIE simulated the formation of air gaps of varying sizes. The air-gap profiles were then input to MARC (a finite element model) to simulate electromigration-induced stress arising from increasing volumetric strain in the aluminum lines. Contour plots were then generated of the maximum principal stress for structures with different air-gap sizes.
In this model, the failure mode studied was SiO2 sidewall cracking at some critical value of the tensile maximum principal stress, acrit(SiO2). Following the methods of Knowlton et al., an approximate MTTF for each air-gap case can be deduced from the critical acrit(Al) required to induce failure [9].
Preliminary experimental electromigration data for two air-gap splits fabricated at Texas Instruments were compared with hydrogen silsequioxane (HSQ) embedded low-k SOD and HDP-CVD SiO2 gap-fill [7]. Data were collected for open failures after 1.75 mA/cm2 at 250?C applied stress. Contrary to the initial modeling results, the lifetime of the air-gap samples - even with a thin sidewall thickness (<100 nm) - were statistically the same as the HDP-CVD SiO2 and the HSQ. Although data for the shorting has not yet been obtained, one would normally expect that cracking of the oxide sidewall and subsequent extrusions would reduce the electromigration back-stress, resulting in faster open failures.
Conclusion
Air gaps can reduce interconnect capacitance by as much as 40-50% for tightly spaced metal lines. This capacitance reduction is comparable to or better than that obtained by most low-k materials currently under investigation. At the same time, the use of air gaps addresses many of the integration and reliability concerns associated with currently investigated low-k materials. Air gaps do present a number of integration and reliability issues of their own, and additional work is needed before this technology can be introduced to manufacturing. However, the work done thus far on air-gap integration shows promising results.
Acknowledgments
The authors would like to thank Somnath Nag, R. Scott List, and Robert Havemann of the Semiconductor Process and Development Center at Texas Instruments for their support. We would also like to acknowledge Tetsuya Ueda of the ULSI Technology Development Center at Matsushita Electronics Corp. and James Fleming of Sandia National Labs for their cooperation in providing original figures from their papers on air-gap technology.
References
1. M. Bohr, "Interconnect Scaling - The Real Limiter to High Performance ULSI," IEEE IEDM Tech. Dig., pp. 241-244, 1995.
2. M.B. Anand, M. Yamada, H. Shibata, "NURA: A Feasible, Gas Dielectric Interconnect Process," Symp. on VLSI Technology, pp. 82, 83, June 1996.
3. S.P. Jeng, R.H. Havemann, M. Chang, "Process Integration and Manufacturability Issues for High Performance Multilevel Interconnect," Proc. Mater. Res. Soc. Symp., pp. 25-31, 1994.
4. B. Shieh, et al., "Air-Gap Formation During IMD Deposition to Lower Interconnect Capacitance," IEEE Electron Device Letters, Vol. 19, No. 1, pp. 16-18, Jan. 1998.
5. T. Ueda, et al., "A Novel Air Gap Integration Scheme for Multi-level Interconnects using Self Aligned Via Plugs," Symp. on VLSI Technology, pp. 46, 47, June 1998.
6. J.G. Fleming, E. Roherty-Osmum, "Use of Air-Gap Structures to Lower Intralevel Capacitance," Proc. DUMIC, pp. 139-145, 1997.
7. B.P. Shieh, et al., "Integration and Reliability Issues for Low Capacitance Air-Gap Interconnect Structures," Proc. IEEE IITC, pp. 125, 126, 1998.
8. Conversation with Per Sverdrup, Dept. of Mechanical Engineering, Stanford University.
9. L.C. Bassman, et al., "Simulation of the Effect of Dielectric Air Gaps on Interconnect Reliability," Proc. Mater. Res. Soc. Symp., San Francisco, pp. 323-328, 1997.
BENJAMIN SHIEH received his BS in electrical engineering and materials science from the University of California, Berkeley, in 1995, and his MS in electrical engineering from Stanford University in 1997. He is working toward a PhD in electrical engineering at Stanford University. His current areas of research involve the characterization and modeling of plasma-CVD deposition processes and the integration of air gaps to reduce IC interconnect capacitance. Stanford University, Stanford, CA 94305; e-mail [email protected], ph 650/725-7062.
KRISHNA C. SARASWAT received his PhD in electrical engineering in 1974 from Stanford University, where he is a professor. He is working on new and innovative materials, device structures, and manufacturing technology of silicon ICs. Currently he is involved in the development of BEST (Beck-End Simulation Tool), an interconnect process simulator. He is a Fellow of IEEE, and a member of The Electrochemical Society, MRS and SID. He has authored or co-authored more than 300 technical papers.
MICHAEL D. DEAL received his AB degree in chemistry from Occidental College in Los Angeles, and his MS and PhD degrees in materials science and engineering from Stanford University. He is a senior research scientist in the Center for Integrated Systems at Stanford University. His current interests include interconnect technologies for advanced Si integrated circuits and the development and application of software tools for the fabrication of semiconductor structures.
JIM MCVITTIE received his BS in electrical engineering from the University of Illinois and his MS and PhD degrees, in the same subject, from Stanford University. His current work focuses on plasma diagnostics, process-induced damage, and development of the Stanford Profile Emulator for Etching and Deposition in IC Engineering (SPEEDIE). He is a senior research scientist at Stanford University`s Center for Integrated Systems and has co-authored more than 150 papers.