New parametric-test technologies meet future production challenges
12/01/1996
Cover Article
Equipment Frontiers
New parametric-test technologies meet future production challenges
Gary Pinkerton, Keithley Instruments, Cleveland, Ohio
Continuing trends in the semiconductor industry are driving the need for more sophisticated production testing tools. These trends include IC scale reduction, increasing die size and wafer diameters, strong growth in semiconductor demand, and the need to reduce start-up times to increase profitability.
Reduction in scale has far-reaching effects. Smaller scale factors mean that ICs are more complex, have thinner critical oxide layers (less than 100 ? thick), smaller transistor channels (channel-lengths down to 0.25 ?m), and higher power densities (up to 15 W/die). As these changes occur, test sensitivity must increase to keep pace. For example, electrical parametric tests that characterize device gate leakage and subthreshold currents become more critical.
As circuit features get smaller and device complexities increase, more test types are needed. Larger wafer diameters also increase the number of tests because there are more test sites/wafer.
Also, growth in demand has resulted in the building and upgrading of many semiconductor fabrication facilities. The greater productivity of these new fabs must be supported by automated parametric testing (APT) systems.
Implications for APT systems
APT systems typically are used in fab front-end processes to test the electrical characteristics of the wafer, as opposed to the functional testing of dies that occurs as part of back-end processes. Generally, parametric testing is performed on special test structures instead of actual devices. Still, the test structures are created by the same processes used to create actual transistors, capacitors, resistors, etc., so they have the same types of metal interconnects, insulating oxides, and polysilicon layers as actual devices. Thus, test structures can be used to characterize the wafer and its underlying production processes.
One currently evolving trend is the tendency to test earlier in the front-end processing to determine whether wafers should be allowed to move on to the next process step. Moving test equipment "upstream" requires a certain amount of reprogramming and implies a need for flexible APT hardware and software that can be easily reconfigured and used where required. Ideally, software should require little setup time so that a parametric test group can focus on providing the control data required for rapid fab startup.
Simultaneously, parametric test suites are getting larger. For example, fabs with deep sub-micron (=0.5 ?m) processes are adding oxide quality tests (QBD, VBD, JRAMP, VRAMP), hot carrier effect characterization, and metallization quality tests, such as the standard wafer-level electromigration accelerated test (SWEAT). Other test options include those for nonvolatile memory device testing (flash memory cells and arrays, EPROMs, and EEPROMs) and wafer level reliability (WLR) tests. WLR tests are increasingly performed in-line because they can reduce the amount of stress testing required.
Smaller device dimensions require APT systems that can make more sensitive measurements of oxide and device leakage currents, often at levels below 1 nA. Also, these systems must measure inter-layer dielectric (ILD) capacitance down to 400 fF, and have 30 ?V repeatability for characterizing conductor resistances and critical dimensions.
Limitations of current technology
Improved APT technologies are needed to meet these needs and help development and manufacturing groups to better monitor and optimize front-end semiconductor processes (Fig. 1). While parametric testing of finished wafers provides valuable data for assessing and controlling the entire process, fabs increasingly find that front-end testing highlights processing problems more quickly.
The increasing number of tests makes high throughput more important than ever. In response to customer needs for higher productivity, APT system designers are focusing on hardware and software issues that once limited test throughput.
One of the problems in the current generation of commercial APT systems is the physical distance of the instruments from the device under test (DUT). Long cables and connectors in the signal path increase measurement noise and have higher parasitic capacitance. These characteristics reduce the sensitivity and accuracy of the measurements. A six-foot cable connecting low level signals to a source-measurement unit (SMU) can also cause oscillation and settling problems.
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Figure 1. Fab production data flow block diagram indicating the pivotal position parametric and wafer-level reliability (WLR) test has in process development.
Another problem with many of these systems is the use of reed relays in the switching matrix. Reed switches are slow relative to many APT system functions. Also, the switch contacts insert a series resistance into the testing path and a voltage potential is generated between the contacts.
Both the cabling and reed switches limit test speed and sensitivity. Parasitic capacitance and resistance reduce test accuracy and increase the required time for a measurement to settle to its actual value. In the past, the number of tests run on each wafer was lower, and sensitivity was less critical. Today, however, fabs are looking for new ways to increase throughput and detect process variations that once were not critical.
An integrated approach
To overcome these limitations, Keithley developed its S600 parametric test system (Fig. 2). The system is an integrated tester designed to perform DC testing of deep submicron CMOS wafers.
It is more sensitive than other parametric test systems, and performs a typical test suite in about a quarter of the time required by the earlier generation of parametric testers. The increase in speed is due to the exceptionally low settling times; the tester settles to within 5% of 1 pA in <100 ms with 0.1 Vdc applied.
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Figure 2. S600 system block diagram showing the design elements that provide lower level current and capacitance measurements with higher throughput and reliability.
As shown in Fig. 3, the design gets rid of the long cable and reed relays that typically connect the test head to an APT system`s instruments. High-performance probe cards interface the DUTs to the tester. These cards have extremely low leakage and low capacitance. Typical probe cards have leakages of 500 fA/V and parasitic capacitances of 50 to 100 pF; the system`s probe cards have leakage currents of < 5 fA/V and just 1 pF of capacitance.
Right behind the probe card are the "pin electronics." Each probing pin has its own amplifier and bias supply located within a centimeter of the DUT. This arrangement eliminates cabling between the test head and the amplifier, reducing the parasitic capacitance and noise associated with the cable. The "per pin" architecture makes it possible to present instrumentation for current/voltage and capacitance measurements to each DUT pin. The design also provides a quiet analog ground connection for a nearly perfect open circuit, ensuring greater measurement integrity.
Parasitic capacitance is reduced all along the measurement path, allowing faster and more accurate gate-oxide and interlayer dielectric capacitance measurements. Specifications are 1% repeatability at 1 pF within 50 ms.
The switching matrix in the system uses solid-state switches instead of reed relays. This increases both the speed and reliability of the system. This 50 W, 100 MHz matrix also provides an impedance-matched, low-loss switching path to the probe pins.
The system`s modular design provides flexibility in configuring source-measure instrumentation. Up to eight source-measure units (SMUs) can be included in the system. This instrumentation takes advantage of the latest analog-to-digital (A/D) conversion technology to achieve maximum speed, accuracy, and stability.
To insure valid measurements, diagnostic software running in the background continuously monitors system health. These diagnostic routines help prevent inaccurate tests that could lead to poor process decisions or costly re-testing. The system diagnostics also help technicians pinpoint faults and increase uptime. Reliability is enhanced further because reed relays have been eliminated and the number of interconnections reduced. All these features translate into higher productivity.
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Figure 3. The S600 parametric test system.
Behind the system design is the latest surface mount technology, multichip modules, plus a wide variety of semiconductor devices that allow a wide range of APT functions to fit within a small footprint.
To further improve productivity, the system sports an improved user interface and simplified methods of creating test programs. These improvements are a result of using the Keithley Test Environment (KTE), a data-oriented programming interface that allows users at any level to create test plans and document results. KTE runs on the new Sun UltraSPARC workstations, so test engineers can quickly develop new measurement algorithms and implement test floor customization and integration by modifying a test sequencer, or adding user subroutines. Wafer descriptions are easily created by documenting subsite, site, and other wafer information. Test plans are generated by documenting subsite test sequences and probing patterns.
Test programs are downloaded to an embedded computer in the tester running a real-time operating system. The embedded computer runs the test and controls the prober. This design ensures that tests will run quickly and allows a single Sun workstation to control several testers without degrading throughput.
The bottom line is productivity
While fabs seek a high level of measurement integrity, ease of use, and reliability, they also expect test equipment systems with greater sensitivity, resolution, and throughput. Often, this means supplying application engineering services that help APT users optimize throughput at high levels of accuracy. These same engineers are also called on to resolve problems that might affect system up-time. In short, APT systems and those who support them must increase the efficiency of fabs, many of whom are hard pressed to keep up with the demand for their products.
For more information, contact GARY PINKERTON at Keithley Instruments Inc., 28775 Aurora Road, Cleveland, OH 44139-1891; ph 800/552-1115, fax 216/248-6168, e-mail: [email protected], internet: http://www.keithley.com.