Fabricating High resolution amel flat panel displays
11/01/1996
Fabricating high resolution AMEL flat panel displays
Martin Aguilera, Brad Aitchison, Planar Systems Inc., Beaverton, Oregon
A new silicon-based design for active-matrix electroluminescent (AMEL) flat panel displays can achieve the high resolutions required for today`s computer applications. The displays boast a dot pitch of only 24 ?m (>1000
lines/in.) and resolutions of 640 ? 480 and 1280 ? 1024 pixels. Each pixel of a display needs its own addressing transistor, a data-hold capacitor, and a high-voltage switching transistor. All row- and column-drivers are also located on the same chip. AMEL displays are fabricated using silicon-on-insulator (SOI) wafers with mostly standard CMOS processing. A refractory metal interconnect is needed to withstand the high temperatures and extended times required for the electroluminescent
(EL)-film deposition process.
As the flat panel display (FPD) market continues to grow, new technologies are being developed to improve the characteristics of today`s widely used liquid crystal displays (LCDs). Though LCDs dominate today`s FPD market, they still have limitations - thus providing opportunities for improvement and innovation. As we shall see in this article, one important recent innovation has been the AMEL display. All of the processing and testing results in a finished display such as that shown in Fig. 1, with the specifications shown in the table.
Among the limitations of conventional LCDs (with an active or passive matrix) are high power consumption, low resolution, low speed, limited viewing angle, high weight, and lack of ruggedness. These constraints have limited the range of possible applications for FPDs.
In addition to LCDs, the most prominent FPD technologies today are the plasma display (PD), EL display, field-emission display (FED) and light-emitting-diode (LED) display. Of these technologies, only the first three currently exist as viable commercial products, while FED and LED displays are still in the research-and-development stage.
The various refined FPD technologies can coexist because they target different applications. For example, PD technology is used mostly for large-area displays (> 20 in. diagonal). The displays are passively driven, and are manufactured on glass substrates. (A passive matrix addresses a row of pixels at a time, as opposed to an active matrix where each pixel is individually addressed). LCDs can be both passive matrix or active matrix, are manufactured on glass substrates, and are used mostly for laptop or notebook computer displays.
EL displays can also be driven in a passive-matrix or active-matrix mode. However, EL displays (because they emit light instead of filtering light) can be manufactured by using an opaque substrate such as a silicon wafer or glass . The choice of substrate depends on the application for which the display is intended. For large, direct-view displays (~10 in. diagonal), glass substrates are used. Silicon-wafer substrates can be used for smaller (~ 2.7 in. diagonal), high-resolution (300 lines/in.) direct-view displays, and for miniature head-mounted displays (HMDs) with higher resolution (1000-2000 lines/in.).
Advantages of silicon
Silicon wafers have many advantages as FPD substrates. In particular, the individual pixel circuitry, along with the display-driver electronics, can be integrated into the same die. Silicon process technology is mature and well understood, while the equipment set available for silicon processing is large, efficient, and cost effective (as compared to glass-processing equipment for large-area flat panels).
Silicon substrates (in conjunction with EL properties) can also solve many of the problems that have plagued LCDs. Specifically, EL displays based on silicon offer high-resolution, low-power operation, wide viewing angle, low weight, and rugged construction. Because of these characteristics, EL displays have been frequently employed for high-performance instrumentation and military applications.
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Unfortunately, the process of creating high-resolution EL flat panel displays on silicon is not trivial - the pixel structure must withstand up to 80-Vac. Carefully designed isolation schemes and signal-processing circuitry are required. Processing typically consists of 1-layer polysilicon and 5-layer metal structures, and a minimum geometry of 1 ?m.
Using this silicon-based EL technology, a group of companies (Planar Systems, David Sarnoff Research Center, and Allied Signal, with support from DARPA) has created the world`s first AMEL high-resolution displays for head-mounted applications. The displays, with formats of 640 ? 480 pixels and 1280 ? 1024 pixels [1, 2], were produced with a resolution of 1000 lines/in. on a SOI wafer substrate. The 1280 ? 1024 pixel display contains more than 2.6 million transistors and 3.9 million capacitors, and measures 1.2 ? 1.0 in.
Thin-film EL technology
EL is the nonthermal conversion of electrical energy into light. Two main types of display devices can be created using EL: the familiar LEDs and high-field EL devices. In a LED, light is generated by electron-hole recombination near a pn junction. By contrast, an EL device`s light is generated by the subsequent de-excitation of color centers that are excited by the impact of high-energy electrons.
In an EL device, the electrons get their energy from a high electric field set up across a light-generating region (usually called "the phosphor") sandwiched between two insulators. The phosphor usually is a high band-gap semiconductor doped with up to 2% rare-earth halides. The dopant is often called a "color center" and is responsible for the characteristic color of the phosphor. Compound materials in the II-VI family have shown the most promise, with much research focused on ZnS, SrS, ZnSe and CaS. Our current displays use ZnS:Tb for green and ZnS:Mn for amber. A full-color display, currently under development, uses SrS:Ce to produce blue light. Figure 2 shows typical light emission spectra for our phosphors.
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Figure 2. Phosphor emission spectra for group II-VI materials and rare-earth dopants used in EL displays. Peak emissions are amber for ZnS doped with Mn, green for ZnS doped with Tb, and blue for SrS doped with Ce. A full-color display will use all three of these phosphors.
Four mechanisms occur in an EL device to generate light:
1. Electrons are sourced from deep-level interface states;
2. The electrons are accelerated by the high electric field in the semiconductor;
3. Once the electrons reach a high enough energy, they can excite a light emission center via collision into a higher state; and
4. The excited centers then de-excite and emit photons.
Those mechanisms are illustrated in Fig. 3. A very detailed description of ZnS EL has been provided [3].
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Figure 3. Light-emission mechanism for EL display. A six-step sequence is illustrated for a ZnS:Mn phosphor: a) tunnel injection of electrons; b) ballistic acceleration of electrons; c) Mn atom impact excitation; d) photon emissions; e) carrier multiplication by lattice impact; and f) carrier capture by interface states. Photon emission by de-excitation occurs in step d, after injection, acceleration, and collisions by electrons. Carriers are multiplied by lattice impact and then captured by the interface states.
Design and fabrication
In an AMEL device, each pixel is addressed individually; therefore the display layout necessarily involves the design of the pixel structure and its addressing circuitry. Display illumination results from a high-voltage analog signal, which must be isolated from the low-voltage digital signals used to address each pixel. Thus, the display operation requires the manipulation of two main signals across the display area. One is the signal that controls the pixel to be either on or off. The other is the high AC voltage needed to accelerate the electrons across the phosphor, causing light emission.
Additional peripheral circuitry consists of the shift registers and line drivers required for addressing the display. The data inputs are delivered via 40 parallel lines, along with six control signals, all with standard 5-V logic levels. For 60-Hz frame rates, the data is transferred at a rate of about 25 MHz.
Due to the high-voltage operation of EL displays, very careful attention must be given to the design of the pixel structure to effectively isolate the high-voltage from the low-voltage circuitry. In addition, care must taken to avoid undesirable parasitic capacitance that could make a given pixel inoperable. Those considerations make the pixel design the most critical structure in the display.
The isolation requirements mandate the use of SOI-wafer substrates. The superior isolation capabilities of SOI wafers make it possible to effectively isolate high-voltage structures from low-voltage ones [4, 5]. Using SOI wafers, we can achieve 12-?m pixel structures, corresponding to a resolution of 2000 lines/in. [6].
Actual display fabrication consists of two operations: the IC process and the EL process. The IC process uses traditional semiconductor fabrication techniques to create the pixel structures, the peripheral driving circuitry, and their interconnects. By contrast, the EL process is used for phosphor deposition, its interconnects and overall device integration, and packaging. Though both operations are demanding, we consider the EL processes more critical due to the phosphor-deposition complexities and the relatively high cost of the wafers at that stage.
Semiconductor IC processing
The AMEL was designed to take advantage of standard CMOS processing as much as possible. We create n-well and p-well regions, islands, source-gate-drain regions, vias, contacts, and metal interconnects. This part of the process uses one polysilicon level and three metal depositions. The current minimum geometries are 1.2 ?m, and gate-oxide thickness is set at about 350 ?. Use of metal layers as electrodes for capacitors, high-voltage shields, and data interconnects results in a high degree of complexity for the metallization steps (Fig. 4).
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Figure 4. Standard CMOS process steps used in fabrication of an AMEL display. Current minimum geometries are 1.2 ?m, and the gate-oxide thickness is around 350 ?.
Two key differences from a standard CMOS process are the use of SOI wafers (and their associated processing requirements) and the need to use refractory metals for the interconnects.
One of the primary complications of SOI technology is that transistors can have up to three gates (Fig. 5). The first, or top, gate is identical to any standard CMOS gate. The second gate, in which the buried oxide acts as the gate oxide, is formed with the bottom silicon substrate. Finally, many SOI transistors use a polywrapped structure, in which the side of the active silicon island becomes a gate [7].
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Figure 5. Structure of SOI transistor. This polywrapped structure can have up to three gates. The top gate is a standard CMOS gate, the bottom gate uses the buried oxide as the gate insulator, while the side gate uses the edge of the active silicon island.
Due to the peculiar multigated structure, it is extremely important to develop a process in which the edge and bottom gates play a minimal role in device operation. In particular, the edge gates need to be eliminated because substandard gate oxides in the corner regions tend to have low breakdown voltage. Most display designers develop proprietary techniques to eliminate that gate.
As noted earlier, refractory metals must be used because of the high temperature (450?C) and long time (16 hr) of the atomic-layer-epitaxy (ALE) process used to deposit the insulator/phosphor/insulator stack. Aluminum interconnects would create hillocks that are likely to damage the transistors and EL stack. Possible options for the conductors include copper, tungsten, and TiW.
After the IC processing stages are completed, the wafers undergo process control monitor (PCM) testing while the individual displays undergo functional testing. The test suite is designed to characterize the electrical performance of the IC (transistor leakage, contact chains, line resistances, etc.), as well as internal self-tests for the functionality of the row- and column-driver structures.
EL processing steps
ALE, which deposits the phosphor stack on the wafers, is central to the EL process. The main advantages of ALE are its pinhole-free and conformal results. Since an AMEL is essentially a large high-voltage capacitor, any pinholes will lead to catastrophic arcing. Arcing tends to propagate, depending on the structure of the insulator/phosphor/insulator stack, thus destroying the entire display. The most effective way to avoid arcing problems is to deposit defect-free EL films by ALE.
ALE, pioneered by Tuomo Suntola [8], is a chemical-vapor-deposition (CVD)-class deposition process. The growth is self-limiting - once the surface is saturated with a given material, the growth stops - so single-atomic-layer film growth is obtained (Fig. 6). For example, the ZnS phosphor can be grown by sequentially passing a vapor of zinc precursor, followed by a sulfur precursor, followed by another zinc precursor, and so on, until the film is the desired thickness.
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Figure 6. ALE deposition mechanism. In the example shown for a ZnS phosphor, layers are deposited by alternating zinc and sulfur precursors. a) The first precursor and carrier gas arrive; b) the surface is filled with the first precursor, and the carrier gas takes the excess material away; c) the second precursor arrives; d) the two precursors react to form the desired material; e) the carrier gas takes the side-products and excess material away; and f) a whole cycle is completed and repeated until the required thickness is achieved.
The AMEL insulators are made of aluminum, titanium, and oxygen in the form of multilayer structures of aluminum oxide and titanium oxide. The multilayer structure improves the breakdown strength of the insulators.
There are many types of ALE reactors based on molecular-beam epitaxy (MBE) or CVD systems. In our system, a "traveling-wave" reactor, solid sources are placed in quartz tubes that are then heated to generate the proper vapor pressure. The sources are then pulsed through the system in a "traveling wave" of vapor. Pulse length is usually less than a second. The high-speed switching of the precursor vapors is the key to this design, and extensive work has been done at Planar International, Espoo, Finland, to optimize the system.
After the wafers are coated with the ALE film, a transparent conductor, indium tin oxide (ITO), is deposited by DC magnetron sputtering to form the top electrode of the EL stack. The ITO and ALE films are then patterned. A high-conductivity metal, aluminum, is then deposited and patterned to finish the interconnects. Fig. 7 shows a scanning electron microscope (SEM) view of the basic device structure.
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Figure 7. SEM view of the cross section for an AMEL pixel.
The individual displays are separated by sawing and a glass cover plate is secured over the display using an optical epoxy. The die is attached to a ceramic carrier, and wire bonds form connections between the two. Next, the wire bonds are encapsulated and a flexible cable is attached.
Once the display has completed IC and EL processing, the next stage is to test its functionality and measure its characteristics in three steps: a phosphor burn-in, an electrical test, and optical characterization.
The phosphor burn-in, which serves to stabilize the phosphor, slowly ramps the AC voltage up to the final operating voltage, where it is held for a period of time. At this point, the display`s voltage/brightness characteristics are measured.
The electrical test evaluates overall circuit functionality. In particular, the data and select scanners are tested for proper signal transmission and pixel control. A variety of pixel patterns are programmed into each display to define pixel characteristics and defect densities.
The final test, an optical characterization, determines the display`s brightness, contrast, and gray-scale parameters.
Future directions
At present, we are producing monochrome displays based on a 24-?m pixel, which yields a resolution of 1000 lines/in. Volume production is planned for spring 1997. A color display is under development, and first prototypes were demonstrated in May.
There are several possible ways to achieve color displays. One method uses color filters to produce a color pattern. Thus, a 1280 ? 1024 pixel white-monochrome display with color filters will produce a 640 ? 480 full-color VGA-standard display [9]. Four pixels (one red, one green, and two blue) are combined to form one full-color pixel (Fig. 8).
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Figure 8. Color filter approach for a full-color AMEL display.
A second method is a color-sequential approach using a field-sequential color shutter. A full-color image is temporally divided into red, green, and blue sub-images. The human eye integrates the temporal color information so that each pixel can appear in many colors. The number of available colors depends on how fast the display is driven. This method preserves the high pixel resolution, but, due to the increased speed, requires more complicated drive electronics.
We are pursuing both approaches, and expect to produce color displays employing both technologies. In addition, we are in the last stages of developing a new 12-?m pixel that will give a resolution of 2000 lines/in. Once completed, it will lead to the highest-resolution display ever created.n
Acknowledgment
This work was supported by the Advance Research Projects Agency Electronic Systems Technology Office (ARPA/ESTO) under contract MDA 972-92-C-0037. The authors are grateful to E. Urban (DARPA/ESTO) and H. Girolamo (US Soldier Systems Command) for encouragement and support. Also, we acknowledge the contributions of the members of the AMEL team at Planar Systems, The David Sarnoff Research Center, Allied/Signal Aerospace, and the members of the Advanced Technology Group at Planar Systems.
References
1. M. Aguilera, L. Arbuthnot, T. Keyser, "First Generation VGA (640 ? 480) Active Matrix Electroluminescent Display for HMD Application," submitted to The International Society for Optical Engineering 10th Annual International AeroSense Symposium, 1996.
2. R. Khormaei, et al., "High Resolution Active Matrix Electroluminescent Display," Society for Information Display Digest, p. 137, 1994.
3. E. Bringuier, J. Appl. Phys., Vol. 75, p. 4291, 1994.
4. G. Dolny, et al., "High Density Active Matrix Electroluminescent Display Using Single Crystal Silicon-on-Insulator High Voltage IC Technology," IEDM Technical Digest, pp. 930-933, 1993.
5. G. Dolny, et al., "The Application Of Silicon-on-Insulator (SOI) Technology for the Fabrication of Fully Scanned Active Matrix Flat Panel Displays," IEEE International SOI Conference Proceedings, p. 97, 1994.
6. L. Arbuthnot, et al., "A 2000 Line-Per-Inch Active Matrix Display," Society for Information Display International Symposium proceedings, p. 374, 1996.
7. H. Hosack, T. Houston, G. Pollack, "SIMOX Silicon-on-Insulator: Materials and Devices," Solid State Technology, Dec. 1990.
8. T. Suntola, Handbook of Crystal Growth, edited by D.T.J. Hurle, Vol. 3, Elsevier Science, 1994.
9. M. Aguilera, et al., "An RGB Color VGA Active-Matrix EL Display," Society for Information Display International Symposium proceedings, p. 125, 1996.
MARTIN AGUILERA received his BA degree in physics from the University of California. He is process manager and lead engineer for Planar`s AMEL development. Planar Systems Inc., 1400 NW Compton Drive, Beaverton, OR 97006, ph 503/690-1100, fax 503/690-6995, e-mail [email protected].
BRAD AITCHISON received a BA degree in physics from Willamette University and an MS degree in materials science engineering from the University of California at Los Angeles. He leads the ALE effort for monochrome AMEL development at Planar.