RTPs Future murky, with application immature
11/01/1996
RTP`s future murky, with applications immature
According to speakers at the recent 4th International Conference on Advanced Thermal Processing of Semiconductors (RTP `96), held in Boise, ID, some RTP processes are now mature, but others require significant improvements.
M.F. Pas of Texas Instruments said that RTP is the only way to achieve the SIA roadmap requirements for silicide contact thickness and junction depth; silicide and implant anneal are mature enough for use in production. Though CoSi2 is being considered for 0.25-micron contacts because of superior sheet resistance and diode leakage, improved understanding of TiSi2 phase transformations suggests, according to Pas, that titanium can be extended to 0.18-micron devices and beyond.
Other applications of RTP are less mature, and requirements are less clear. Pas claimed that RTP will only displace batch furnaces where it is an enabling technology (as it is for silicide and implant anneal), or where it provides lower defect density and lower cost of ownership (COO) than the equivalent batch process. Thus, RTP throughput, power consumption, and other cost factors must be improved.
Hitachi`s Yoshikazu Tanabe points out that while all current applications of RTP are really annealing processes in one form or another (see table), many proposed high-k dielectrics for DRAM storage cells are thermally unstable and will require further thermal budget reductions. Nitrided oxide is also a promising candidate for thin gate dielectrics. So, he said, "it is likely that the next important application of RTP will be gate dielectric and capacitor dielectric processing."
Both Pas and J.R. Hauser, of North Carolina State University, concur. They note that existing problems with boron penetration of the gate oxide during gate implant will become more severe as oxides get thinner. Hauser suggested that metal gates will eventually be required. Meanwhile, RTCVD nitridation and oxidation are frequently suggested, but are constrained by both thermal budget and throughput. According to Pas, high temperature (>1000?C) RTCVD is not reasonable for thermal budget reasons, but lower temperature growth offers unacceptably low deposition rates. Furthermore, said Tanabe, higher deposition rates tend to degrade RTCVD quality. RTP is thus unlikely to be manufacturable for steps requiring more than 100 ? of oxide.
Both Tanabe and Pas foresee increased use of single wafer processing for large diameter wafers. Si becomes more viscous at temperatures >1000?C, and is thus more susceptible to sagging and slip dislocations. Single wafer systems can support the wafer more easily, and shorter process time prevents dislocation migration. Still, Pas said, larger wafers will present serious problems because dopant variations are more likely over the larger area, and can have a major effect on device properties as dimensions shrink.
While throughput and COO are serious worries for present RTP applications, Hauser said temperature measurement and control is "the most pressing problem and the most elusive one" for future applications. For example, future devices will require extremely steep dopant profiles - the upper channel should be lightly doped for threshold control and advanced mobility; the middle region should be more heavily doped to prevent punch through; and the lower channel should have moderate doping to reduce capacitance. The statistical nature of ion implant will make it difficult or impossible to achieve these profiles, so epitaxy or selective epitaxy will probably be needed to form them, and extremely low thermal budgets (as low as 800-850?C) will be required to preserve them through subsequent processes. Similarly, extremely shallow junctions may be formed by elevating the source/drain region through selective epitaxy. All of these proposals will require tight control of interface properties, and thus will probably require single wafer rapid thermal processes. - K.D.